Structure and method for implementing hierarchical routing pools in a programmable logic circuit
AssigneeLattice Semiconductor Corporation
InventorsCyrus Y. Tsui, Ju Shen, Chanchi J. Cheng, Ming C. Hsu
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Abstract
A programmable logic device has multiple groups of generic logic blocks. Each group of generic logic blocks is interconnected by a local routing pools. A global routing pool is provided to interconnect the local routing pools. The global and local routing pools can be implemented in volatile or non-volatile technology, such as E.sup.2 PROM technology. The programmable logic device can also be implemented as an in-system programmable logic device.
Claims12
In a complex PLD, a programmable interconnection system for interconnecting programmable logic blocks comprising:
- a first programmable interconnection circuit for interconnecting a first group of programmable logic blocks, said first programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said first group;
- a second programmable interconnection circuit for interconnecting a second group of programmable logic blocks, said second group of programmable logic blocks being separate and distinct from said first group of programmable logic blocks, said second programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said second group;
- and
- a third programmable interconnection circuit for interconnecting said first and second programmable interconnection circuits.
A method in a programmable interconnection system for interconnecting programmable logic blocks comprising:
- interconnecting a first group of programmable logic blocks using a first programmable interconnection circuit, said first programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said first group;
- interconnecting a second group of programmable logic blocks using a second programmable interconnection circuit, said second group of programmable logic blocks being separate and distinct from said first group of programmable logic blocks, said second programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said second group;
- and
- interconnecting said first and second programmable interconnection circuits using a third programmable interconnection circuit.
Dependencies are inferred from the claim text.