Apparatus and method to improve programming speed of field programmable gate arrays

An apparatus for transferring a configuration bitstream from a data source to a Field Programmable Gate Array comprising:

• a shift register, located on the Field Programmable Gate Array, operable to receive the configuration bitstream from the data source, means, coupled to the shift register,
• (a) for receiving a signal having a first or second logic state from the data source,
• (b) for enabling the shift register to receive N bits of the configuration bitstream in a clock cycle and for enabling each of the bits of the configuration bitstream received by the shift register to shift N bits per clock cycle when said signal is in said first logic state;
• and
• (c) for enabling the shift register to receive one bit of the configuration bitstream in a clock cycle and for enabling each bit of the configuration bitstream received by the shift register to shift one bit per clock cycle when said signal is in said second logic state.

A method for reducing the size of a configuration bitstream for a Field Programmable Gate Array, comprising the steps of:

• (a) receiving a configuration bitstream,
• wherein said configuration bitstream is comprised of frames, wherein said frames include control bits, address bits and data bits, said data bits to be written into an address location in a switching array of the Field Programmable Gate Array at a location indicated by said address bits;
• wherein said control bits of each frame have a compress bit, and
• wherein said compress bit has a first or a second logic state;
• (b) receiving a frame of the configuration bitstream with said compress bit in said first logic state;
• (c) writing data bits to an address location of said switching array specified by said address bits of said received frame;
• (d) receiving a frame of the configuration bitstream with said compress bit in said second logic state;
• (e) writing data bits, associated with the previous frame received when the compress bit was in said first logic state, to an address location in said switching array specified by said address bits of said received frame of step (d), wherein in said received frame of step (d) has no data bits.

A method for reducing the size of a configuration bitstream for a Field Programmable Gate Array, comprising the steps of:

• (a) receiving a configuration bitstream,
• wherein said configuration bitstream is comprised of frames,
• wherein said frames include control bits, address bits and data bits, said data bits to be written to an address in a switching array of the Field Programmable Gate Array at an address indicated by said address bits;
• wherein said control bits of each frame have an increment bit, and
• wherein said increment bit has a first or a second logic state;
• (b) receiving a frame of the configuration bitstream with said increment bit in said first logic state,
• (c) writing data bits of said received frame to an address of said switching array specified by said address bits;
• (d) receiving a second frame of the configuration bitstream with said increment bit in said second logic state,
• (e) incrementing said address by a predetermined number;
• and
• (f) writing data bits of said second frame to said incremented address of said switching array, wherein said second frame of the configuration bitstream includes no address bits.