High voltage charge pump and related circuitry

An integrated circuit, comprising:

• a memory;
• wherein said memory comprises:
• voltage elevating means (51) for receiving an input voltage having a first predetermined voltage level and for providing an intermediate voltage having a second predetermined voltage level, wherein the second predetermined voltage level is higher potential than the first predetermined voltage level;
• clock voltage level shifting means (53) for receiving a first input clock signal having a maximum voltage level substantially equal to the first predetermined voltage level, for receiving the intermediate voltage, and for providing a shifted clock signal having a maximum voltage level substantially equal to the second predetermined voltage level, said clock voltage level shifting means being coupled to said voltage elevating means;
• clock separating means (55) for receiving the shifted clock signal, for receiving the intermediate voltage, and for providing at least one output clock signal, said clock separating means being coupled to said voltage elevating means and to said clock voltage level shifting means;
• and
• charge pump circuitry (57) for receiving the at least one output clock signal and for providing an output voltage having a third predetermined voltage level, wherein the third predetermined voltage level is higher potential than the second predetermined voltage level, said charge pump circuitry being coupled to said clock separating means.

A circuit for receiving a first voltage and for providing a second voltage wherein the second voltage is higher potential than the first voltage, the circuit comprising:

• a first capacitive element (121), having a first electrode, and having a second electrode for receiving a clock signal;
• a first transistor (103) having a first current electrode coupled to a first voltage terminal for receiving the first voltage, having a second current electrode coupled to the first electrode of said first capacitive element, and having a gate electrode;
• a second capacitive element (122), having a first electrode coupled to the gate electrode of said first transistor, and having a second electrode for receiving a negated clock signal;
• a second transistor (105) having a first current electrode coupled to the first voltage terminal for receiving the first voltage, having a second current electrode coupled to the first electrode of said second capacitive element, and having a gate electrode coupled to the first electrode of said first capacitive element;
• a third capacitive element (123), having a first electrode, and having a second electrode for receiving the clock signal;
• a third transistor (109) having a first current electrode coupled to the gate electrode of said first transistor, having a second current electrode coupled to the first electrode of said third capacitive element, and having a gate electrode;
• a fourth capacitive element (124), having a first electrode coupled to the gate electrode of said third transistor, and having a second electrode for receiving the negated clock signal;
• and
• a fourth transistor (111) having a first current electrode coupled to the gate electrode of said second transistor, having a second current electrode coupled to the first electrode of said fourth capacitive element, and having a gate electrode coupled to the first electrode of said third capacitive element, the gate electrode of said fourth transistor being coupled to a node which provides the second voltage.