Substrate bias generating circuit

A substrate bias generating circuit, comprising:

• a voltage-to-current converter, comprising:
• a differential amplifier having first and second bipolar transistors and a current mirror, a collector of each of the first and second bipolar transistors coupled to the current mirror, and emitters of the first and second bipolar transistors coupled together, a base of said first bipolar transistor for receiving a bandgap generated reference voltage;
• a first P-channel transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to a collector of said first bipolar transistor, and a second current electrode coupled to a base of the second bipolar transistor, said first P-channel transistor providing a first current;
• and
• a first resistor having a first terminal coupled to said second current electrode of said first P-channel transistor, and a second terminal coupled to a second power supply voltage terminal;
• a second P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode, said second P-channel transistor providing a second current;
• a third P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode;
• a voltage level sensing circuit, comprising:
• a second resistor having a first terminal coupled to said second current electrode of said second P-channel transistor, and a second terminal;
• a third resistor having a first terminal coupled to said second terminal of said second resistor, and a second terminal, a first voltage drop across said third resistor is directly proportional to a second voltage drop across said first resistor for compensating for temperature and process variations of said first resistor;
• and
• a first N-channel transistor having a first current electrode coupled to said second current electrode of said third P-channel transistor, a control electrode coupled to said second terminal of said second resistor, and a second current electrode coupled to a second power supply voltage terminal;
• a second N-channel transistor having a first current electrode coupled to said second terminal of said third resistor, a control electrode coupled to said second terminal of said third resistor, and a second current electrode for receiving a substrate bias voltage, said second N-channel transistor for compensating for temperature and process variations of said first N-channel transistor;
• an oscillator having an input terminal coupled to said first current electrode of said first N-channel transistor, and an output terminal, said oscillator for producing a series of pulses at a predetermined frequency;
• and
• a charge pump having an input terminal coupled to said output terminal of said oscillator for receiving said series of pulses, and an output terminal for providing said substrate bias voltage.

A substrate bias generating circuit for providing a substrate bias voltage, comprising:

• a differential amplifier having a first input terminal for receiving a reference voltage, a second input terminal, and an output terminal;
• a first current source having a first terminal coupled to a first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal coupled to said second input terminal of said differential amplifier, said first current source for providing a first current;
• a second current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal for providing a second current;
• a first resistor having a first terminal coupled to said second terminal of said first current source for receiving said first current, and a second terminal coupled to a second power supply voltage terminal;
• a second resistor having a first terminal coupled to said second terminal of said second current source, and a second terminal;
• a third resistor having a first terminal coupled to said second terminal of said second resistor, and a second terminal, said third resistor for receiving said second current, and compensating for temperature and process variations of said first resistor;
• a first MOS transistor having a first current electrode and a control electrode both coupled to said second terminal of said third resistor, and a second current electrode for receiving said substrate bias voltage;
• a third current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal for providing a third current;
• a second MOS transistor having a first current electrode coupled to said second terminal of said third current source, a control electrode coupled to said second terminal of said second resistor, and a second current electrode coupled to said second power supply voltage terminal, said second MOS transistor for compensating for temperature and process variations of said first MOS transistor;
• an oscillator having an input terminal coupled to said first current electrode of said fourth MOS transistor, and an output terminal, said oscillator for producing a series of pulses at a predetermined frequency;
• and
• a charge pump having an input terminal coupled to said output terminal of said oscillator for receiving said series of pulses, and an output terminal for providing said substrate bias voltage.