Circuit for eliminating off-chip to on-chip clock skew

A method for eliminating clock skew between an off-chip clock signal originating off the integrated circuit and an on-chip clock signal produced on the integrated circuit, the method comprising the steps of:

• (a) receiving the off-chip clock signal and phase delaying the off-chip clock signal an amount to produce the on-chip clock signal including the substeps of:
• (a.1) in a first delay path, phase delaying the off-chip clock signal the amount of phase delay, phase delay through the first delay path being adjustable,
• (a.2) in a second delay path, phase delaying the off-chip clock signal the amount of phase delay, phase delay through the second delay path being adjustable, the off-chip clock signal being phased delayed an identical amount at an output of the first delay path as at an output of the second delay path, except when phase delay through the first delay path or through the second delay path is being adjusted, and
• (a.3) selecting one of the first delay path and the second delay path to produce the on-chip clock signal including the substeps of selecting the first delay path when phase delay through the second delay path is adjusted and selecting the second delay path when phase delay through the first delay path is adjusted;
• (b) generating control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, whether and how to change the amount of phase delay by which the phase delay means delays the off-chip clock signal to produce the on-chip clock signal;
• and,
• (c) varying the amount of phase delay in step (a) based on the control signals generated in step (b).

A circuit on an integrated circuit for eliminating clock skew between an off-chip clock signal originating off the integrated circuit and an on-chip clock signal produced on the integrated circuit, the circuit comprising:

• phase delay means for receiving the off-chip clock signal and phase delaying the off-chip clock signal an amount to produce the on-chip clock signal, the phase delay means including
• a first delay path for phase delaying the off-chip clock signal the amount of phase delay, phase delay through the first delay path being adjustable,
• counter means, coupled to the phase delay means, for generating a phase delay value, the phase delay value determining the phase delay through the first delay path, wherein the counter means generates the phase delay value on a plurality of digit outputs, each digit output representing an order of magnitude of delay, and
• control means coupled to the phase delay means and the counter means for causing the counter means to increment and decrement the phase delay value based on the control signals;
• a second delay path for delaying the off-chip clock signal the amount of phase delay, phase delay through the second delay path being adjustable, the off-chip clock signal being phased delayed an identical amount at an output of the first delay path as at an output of the second delay path, except when phase delay through the first delay path or through the second delay path is being adjusted, and
• selection means, coupled to the first delay path and the second delay path, for selecting one of the first delay path and the second delay path to produce the on-chip clock signal;
• and,
• phase detector means, coupled to the phase delay means, for receiving the off-chip clock signal and the on-chip clock signal and generating control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, whether and how to adjust the amount of phase delay by which the phase delay means delays the off-chip clock signal to produce the on-chip clock signal;
• wherein when phase delay through the first delay path is adjusted, the selection means selects the second delay path and when phase delay through the second delay path is adjusted the selection means selects the first delay path.

A method for eliminating clock skew between an off-chip clock signal originating off the integrated circuit and an on-chip clock signal produced on the integrated circuit, the method comprising the steps of:

• (a) receiving the off-chip clock signal and phase delaying the off-chip clock signal an amount to produce the on-chip clock signal including the substeps of
• (a.1) in a first delay path, phase delaying the off-chip clock signal the amount of phase delay, phase delay through the first delay path being adjustable,
• (a.2) generating a phase delay value, the phase delay value determining the phase delay through the first delay path, wherein the phase delay value is generated on a plurality of digit outputs, each digit output representing an order of magnitude of delay,
• (a.3) incrementing and decrementing the phase delay value based on control signals,
• (a.4) in a second delay path, phase delaying the off-chip clock signal the amount of phase delay, the off-chip clock signal being phased delayed an identical amount at an output of the first delay path as at an output of the second delay path, except when phase delay through the first delay path or through the second delay path is being adjusted, and
• (a.5) selecting one of the first delay path and the second delay path to produce the on-chip clock signal including the substeps of selecting the first delay path when phase delay through the second delay path is adjusted and selecting the second delay path when phase delay through the first delay path is adjusted;
• (b) generating the control signals based on phase difference between the off-chip clock signal and the on-chip clock signal;
• and,
• (c) varying the amount of phase delay in step (a) based on the control signals generated in step (b).