Circuit arrangement for genrating square-shaped signals

Abstract

A first input signal has successive zero amplitude crossings. A first comparator generates a first bilevel output signal responsive to the first input signal. The first comparator has a hysteresis characteristic which is switched on at each said zero crossing of the first input signal and switched off prior to each occurrence of the next following zero crossing. A second input signal has successive zero amplitude crossings and is displaced in phase relative to the first input signal. A second comparator generates a second bilevel output signal responsive to the second input signal. The hysteresis characteristic is switched on by level transitions of the first bilevel output signal and switched off by level transitions of the second bilevel output signal. The first and second input signals may be sinusoidal. The hysteresis characteristic may controlled by first and second flip/flops, which are set by the first bilevel output signal and reset by the second bilevel output signal.

Dependencies are inferred from the claim text.