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US 5,394,012 AGranted
Semiconductor device and manufacturing method of the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHiroshi Kimura
Life of this patent
Estimating the term…
Abstract
Source/drain diffusion regions are formed at a surface of a silicon substrate, which is substantially flat and has a first surface roughness. Surfaces of the source/drain diffusion regions are covered with a polysilicon film having a surface which has a second surface roughness larger than the first surface roughness. The polysilicon film is removed by etching to expose the surfaces of the source/drain diffusion regions. Owing to this etching for removal, the surfaces of the source/drain diffusion regions have a third surface roughness larger than the first surface roughness.
Claims16
An interconnection structure of a semiconductor device, comprising:
- a semiconductor substrate having a main surface having a first surface roughness;
- a conductive region formed in the main surface of said semiconductor substrate and having a surface portion which has a second surface roughness larger than said first surface roughness;
- an insulating layer formed on said conductive region and having an opening reaching said surface portion having the second surface roughness;
- a conductive layer formed on a sidewall of said opening of said insulating layer;
- and
- an interconnection layer formed to be in contact with said surface portion of said conductive region having the second surface roughness, and formed of a material different from the material of said conductive layer.
3 more elements
An interconnection structure of a semiconductor device, comprising:
- a semiconductor substrate having a main surface having a first surface roughness;
- a conductive region formed in the main surface of said semiconductor substrate and having a surface portion which has a second surface roughness larger than said first surface roughness;
- an insulating layer formed on said conductive region and having an opening reaching said surface portion having the second surface roughness;
- and
- an interconnection layer of a conductive material formed on sidewall of said opening of said insulating layer to be in contact with said surface portion having the second surface roughness of said conductive region;
- wherein
- the region of said interconnection layer on the main surface of said semiconductor substrate has a prescribed width, and the surface portion of said conductive region having the second surface roughness which is in contact with said interconnection layer extends below the main surface of said semiconductor substrate and has a width which is larger than the prescribed width of said interconnection layer.
4 more elements
An interconnection layer of a semiconductor device, comprising:
- a semiconductor substrate having a main surface having a first surface roughness;
- a conductive region formed in the main surface of said semiconductor substrate which has a surface portion having a second surface roughness which is larger than said first surface roughness;
- an insulating layer formed on said conductive region and having an opening reaching said surface portion having the second surface roughness;
- and
- an interconnection layer formed on said insulating layer to be in contact with the surface portion having the second surface roughness of said conductive region through said opening;
- wherein
- said second surface roughness is defined by unevenness at the surface portion of said conductive region, distance between adjacent protruding portions of said unevenness being within the range of from 10 nm to 200 nm, and difference in level between adjacent protruding and depressed portions of said unevenness being within the range of from 5 nm to 100 nm.
4 more elements
A semiconductor device, comprising:
- a semiconductor substrate having a main surface having a first surface roughness;
- a conductive region formed in the main surface of said semiconductor substrate;
- a conductive layer formed to be in contact with said conductive region and having a surface portion which has a second surface roughness larger than said first surface roughness;
- an insulating layer formed on said conductive layer and having an opening reaching the surface portion having the second surface roughness of said conductive layer;
- an interconnection layer formed on said insulating layer to be in contact with the surface portion having the second surface roughness of said conductive layer through said opening;
- wherein
- said second surface roughness is defined by unevenness of the surface portion of said conductive layer, distance between adjacent protruding portions of said unevenness being within the range of from 10 nm to 200 nm, and difference in level between adjacent protruding and depressed portions of said unevenness being within the range of from 5 nm to 100 nm.
4 more elements
Dependencies are inferred from the claim text.