Semiconductor integrated circuit device
AssigneesHitachi, Ltd., Texas Instruments Incorporated
InventorsYutaka Ito, Toshiyuki Sakuta, Takumi Nasu
Life of this patent
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Abstract
A semiconductor integrated circuit device with high power noise immunity and high substrate surge immunity. An LOC lead frame to be connected to a power wiring for supplying a source voltage and a ground potential to input circuits of a semiconductor chip is isolated from another LOC lead frame for supplying the source voltage and the ground potential to other circuits. The source voltage and the ground potential for the circuit are supplied by way of external terminals formed by the respective lead frames. Further, the isolated LOC lead frames are connected to each other through a resistive impedance component formed on the semiconductor chip.
Claims30
A device comprising:
- a semiconductor chip;
- a first lead frame to be connected to a power supply wiring for supplying a source voltage or a ground potential to an input circuit formed in said semiconductor chip;
- and
- a second lead frame isolated from said first lead frame for supplying a source voltage or a ground potential to circuits formed in said semiconductor chip other than the input circuit,
- wherein each of said first and second lead frames includes an external terminal for supplying the source voltage or the ground potential to said input circuit and said other circuits;
- impedance means formed on said semiconductor chip for connecting said first and second lead frames to each other and providing a noise filter and a surge buffer;
- wherein said impedance means includes a power wiring conductor for said input circuit and a metal wiring formed integrally with the power wiring conductor for said other circuits.
A device comprising:
- a semiconductor chip;
- a first lead frame to be connected to a power supply wiring for supplying a source voltage or a ground potential to an input circuit formed in said semiconductor chip;
- and
- a second lead frame isolated from said first lead frame for supplying a source voltage or a ground potential to circuits formed in said semiconductor chip other than the input circuit,
- wherein each of said first and second lead frames includes an external terminal for supplying the source voltage or the ground potential to said input circuit and said other circuits;
- impedance means formed on said semiconductor chip for connecting said first and second lead frames to each other and providing a noise filter and a surge buffer;
- wherein said impedance means includes a plurality of metal wiring layers, and
- each of said metal wiring layers includes a low-resistance metal conductor upper layer formed contiguously with a power wiring conductor for the input circuit and a power wiring conductor for said other circuits, and a lower layer providing a refractory metal conductor connected to said upper layer by a plurality of through-holes or vias.
A semiconductor integrated circuit device comprising:
- a first LOC lead frame to be connected to a power wiring for supplying a source voltage or a ground potential to an input circuit formed in a semiconductor chip;
- a second LOC lead frame isolated from said first LOC lead frame for supplying a source voltage or a ground potential to circuits formed in said semiconductor chip other than said input circuit;
- and
- resistance means formed on said semiconductor chip for resistively connecting said first and second LOC lead frames to each other;
- further comprising a capacitor interposed between the power wirings for supplying the source voltage and the ground potential for the input circuit;
- wherein said capacitor is a parasitic capacitor structured such that the source voltage line for the input circuit and the ground line for the circuit are arranged adjacently to each other on said semiconductor chip.
A semiconductor integrated device, comprising:
- a semiconductor chip;
- a first lead to be connected to a first wiring for supplying a first potential to an input circuit formed in said semiconductor chip;
- a second lead to be connected to a second wiring for supplying said first potential to circuits formed in said semiconductor chip other than the input circuit, wherein said second lead is physically isolated from said first lead;
- a first connecting means electrically connecting said first lead to said first wiring;
- a second connecting means electrically connecting said second lead to said second wiring;
- an impedance means formed in said semiconductor chip for electrically connecting said first wiring to said second wiring.
A semiconductor integrated circuit device, comprising:
- a semiconductor substrate;
- a first lead to be connected to a first wiring for supplying a first potential to an input circuit formed on said semiconductor substrate;
- a second lead to be connected to a second wiring for supplying said first potential to circuits formed on said semiconductor substrate other than said input circuit, wherein said second lead is physically isolated from said first lead;
- a first connecting means electrically connecting said first lead to said first wiring;
- a second connecting means electrically connecting said second lead to said second wiring;
- and
- a resistance element formed on said semiconductor substrate for resistively connecting said first wiring to said second wiring, and wherein said first and said second lead each extends over said semiconductor substrate.
A semiconductor integrated circuit device comprising:
- a semiconductor chip;
- first and second lead frames to be connected to first power supply wirings for supplying first and second supply potentials, respectively, to an input circuit formed in said semiconductor chip, said first and second power supply potentials being different in level from each other;
- third and fourth lead frames physically isolated from said first and second lead frames to be connected to second power supply wirings for supplying the first and second supply potentials, respectively, to circuits formed in said semiconductor chip other than said input circuit;
- a first and a second impedance means formed on said semiconductor chip for connecting said first and said third lead frame and connecting said second and said fourth lead frame, respectively;
- wherein each of said first, second, third and fourth lead frames includes an external terminal for supplying a respective one of said first and second supply potentials to a respective one of said input circuit and said other circuits.
A semiconductor integrated circuit device, comprising:
- a semiconductor substrate;
- an input circuit and an output circuit formed on said semiconductor substrate;
- a first lead to be connected to a first wiring for supplying a first potential to said input circuit and formed on said semiconductor substrate, and a second lead to be connected to a second wiring for supplying said first potential to said output circuit and formed on said semiconductor substrate;
- a first bonding pad electrically connected to said first wiring and a second bonding pad electrically connected to said second wiring;
- a first connecting means connecting said first lead to said first bonding pad, and a second connecting means connecting said second lead to said second bonding pad;
- and
- an impedance means formed on said semiconductor substrate for electrically connecting said first wiring to said second wiring.
A semiconductor integrated circuit device, comprising:
- a semiconductor chip;
- a first lead to be connected to a first wiring for supplying a first potential to an input circuit formed in said semiconductor chip;
- a second lead physically isolated from said first lead and to be connected to a second wiring for supplying said first potential to circuits formed in said semiconductor chip other than the input circuit;
- a first connecting means electrically connecting said first lead to said first wiring;
- a second connecting means electrically connecting said second lead to said second wiring;
- and
- a switching element formed in said semiconductor chip and connected between said first wiring and said second wiring.
Dependencies are inferred from the claim text.