Semiconductor memory device containing junction field effect transistor

A dynamic semiconductor memory device including junction field effect transistors and capacitors, comprising:

• a semiconductor substrate having a main surface;
• a plurality of word lines formed electrically isolated from one another on the main surface of said semiconductor substrate and composed of an impurity region of a first conductivity type extending in a first direction;
• a plurality of bit lines formed on said plurality of word lines and extending in a second direction intersecting said first direction;
• and
• a plurality of memory cells disposed at points of intersection between said plurality of word lines and said plurality of bit lines;
• said memory cells each comprising one of said junction field effect transistors and one of said capacitors;
• said junction field effect transistors each containing a gate region and an impurity region of a second conductivity type, said gate region being formed of an impurity region of a first conductivity type connected to said word line, said impurity region of said second conductivity type being formed on the main surface of said semiconductor substrate so as to contact said gate region;
• said impurity region of the second conductivity type including a channel region, a first region and a second region, said channel region being interposed between said first and second regions with a predetermined distance;
• said plurality of bit lines being each formed so as to contact said second region;
• wherein a junction depth of said channel region relative to said gate region is less than a junction depth of each of said first and second regions relative to said gate region;
• and
• each of said capacitors comprises a first electrode in contact with said first region, a dielectric film formed on said first electrode, and a second electrode formed on said dielectric film, wherein said first electrode is formed above said channel region and above an insulating sidewall spacer, a bottom of said sidewall spacer which is in contact with the channel region having a horizontal thickness, and the length of the channel region is equal to said horizontal thickness of said insulating sidewall spacer.