US 5,393,702 A · Via sidewall SOG nitridation for via filling

Abstract

A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer. A silicon nitride cap is formed on the exposed surfaces of the spin-on-glass layer within the via openings to prevent outgassing from the intermetal dielectric layer, and thus to prevent poisoned via metallurgy. A second metal layer is deposited overlying the intermetal dielectric layer and within the via openings and fabrication of the integrated circuit is completed.

Claims11

Dependent claims

The method of forming the intermetal dielectric layer of an integrated circuit while preventing outgassing from said intermetal dielectric layer comprising:

providing a thick insulating layer over semiconductor device structures in and on a semiconductor substrate;
depositing a first metal layer over said thick insulating layer;
etching said first metal layer using photolithography and etching techniques to form the desired metal pattern on the surface of said thick insulating layer;
forming said intermetal dielectric layer comprising:
covering said patterned first metal layer with a first layer of silicon oxide;
covering said first silicon oxide layer with a layer of spin-on-glass material and baking and curing said spin-on-glass layer to form a spin-on-glass silicon oxide layer;
and
covering said spin-on-glass layer with a second layer of silicon oxide to complete said intermetal dielectric layer;
forming via openings through said intermetal dielectric layer to underlying said patterned first metal layer which thereby exposes portions of said spin-on-glass silicon oxide layer;
forming a silicon nitride material cap of between about 50 to 200 Angstroms on the said exposed surfaces of said spin-on-glass silicon oxide layer within said via opening by exposing said spin-on-glass layer to nitrogen atoms at a temperature of between about 450.degree. to 600.degree. C. to prevent said outgassing from said intermetal dielectric layer;
depositing a second metal layer overlying said intermetal dielectric layer and within said via openings;
and
completing fabrication of said integrated circuit.

10 more elements

The method of forming the intermetal dielectric layer of an integrated circuit while preventing outgassing from said intermetal dielectric layer comprising:

depositing a layer of polysilicon over the surface of a semiconductor substrate;
etching said polysilicon layer using photolithography and etching techniques to form the desired pattern of gate electrodes on the surface of said semiconductor substrate;
covering said pattern of gate electrodes with a thick insulating layer;
depositing a first metal layer over said thick insulating layer;
etching said first metal layer using photolithography and etching techniques to form the desired metal pattern on the surface of said thick insulating layer;
forming said intermetal dielectric layer comprising:
covering said patterned first metal layer with a first layer of silicon oxide;
covering said first silicon oxide layer with a layer of spin-on-glass material, and baking and curing said spin-on-glass layer to form a spin-on-glass silicon oxide layer;
and
covering said spin-on-glass silicon oxide layer with a second layer of silicon oxide to complete said intermetal dielectric layer;
forming via openings through said intermetal dielectric layer to underlying said patterned first metal layer which thereby exposes portions of said spin-on-glass silicon oxide;
forming a silicon nitride material cap of between about 50 to 200 Angstroms on the said exposed surfaces of said spin-on-glass silicon oxide layer within said via opening by exposing said spin-on-glass layer to nitrogen atoms at a temperature of between about 450.degree. to 550.degree. C. to prevent said outgassing from said intermetal dielectric layer;
depositing a second metal layer overlying said intermetal dielectric layer and within said via openings;
and
completing fabrication of said integrated circuit.

12 more elements

Dependencies are inferred from the claim text.

Via sidewall SOG nitridation for via filling

Life of this patent

Via sidewall SOG nitridation for via filling

Life of this patent

Abstract

Claims11