Method of making tapered poly profile for TFT device manufacturing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChwen-Ming Liu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChwen-Ming Liu
Estimating the term…
A new method of forming a tapered polysilicon etching profile in the manufacture of a thin film transistor integrated circuit is described. A layer of polysilicon is deposited over the surface of a semiconductor substrate. Ions are implanted into the polysilicon layer whereby the upper half of the polysilicon layer is damaged by the presence of the ions within the layer. The polysilicon layer is anisotropically etched. The polysilicon layer is isotropically etched whereby the damaged upper portion of the layer is etched faster than is the undamaged lower portion resulting in a tapered polysilicon layer. A layer of gate oxide is deposited over the surface of the tapered polysilicon layer. Then the thin film transistor body is formed. A layer of amorphous silicon is deposited over the surface of the gate oxide layer. The amorphous silicon layer is recrystallized to yield larger grain sizes. Channel and source/drain regions are formed within the recrystallized amorphous silicon layer to complete formation of the thin film transistor body. An insulating layer is deposited over the thin film transistor body and the silicon substrate. Contact openings are made through the insulating layer to the source/drain regions and filled with a conductive material to complete the contacts completing the formation of the thin film transistor integrated circuit.
The method of forming a thin film transistor integrated circuit with a tapered polysilicon profile comprising:
The method of claim i wherein said ions implanted into said polysilicon layer are arsenic ions with a dosage of between about 1 E 15 to 3 E 15 atoms/cm.sup.2 and energy of between about 10 to 30 KeV wherein said energy is adjusted so that the projected depth of said ions is within said upper half of said polysilicon layer.
The method of forming a thin film transistor integrated circuit with a tapered polysilicon profile comprising:
Dependencies are inferred from the claim text.