Method for forming a compact transistor structure

A method for forming a transistor comprising the steps of:

• providing a semiconductor substrate;
• forming a conductive interconnect layer overlying the substrate, the conductive interconnect layer having an opening formed therethrough to define a first portion of the conductive interconnect layer and a second portion of the conductive interconnect layer wherein the first the second portions of the conductive interconnect layer are physically separated from one another by the opening, the opening defining a first sidewall of the conductive interconnect layer adjacent the first portion and a second sidewall of the conductive interconnect layer adjacent the second portion;
• forming a conductive region within the opening and laterally adjacent each of the first and second sidewalls of the conductive interconnect layer;
• forming a first current electrode in the conductive region, the first current electrode being electrically coupled to the first portion of the conductive interconnect layer via the first sidewall of the conductive interconnect layer;
• forming a second current electrode in the conductive region, the second current electrode being electrically coupled to the second portion of the conductive interconnect layer via the second sidewall of the conductive interconnect layer, the first and second current electrodes being separated by a channel region within the conductive region wherein the channel region is coupled to the substrate;
• forming a gate dielectric overlying the channel region;
• and forming a gate electrode overlying the gate dielectric.

A method for forming a transistor comprising the steps of:

• providing a semiconductor substrate having a surface;
• forming a first conductive portion overlying the substrate and having a sidewall which faces an opening which exposes the surface of the substrate;
• forming a second conductive portion overlying the substrate and having a sidewall which faces the opening the first and second conductive portions being separated;
• forming a conductive region within the opening, electrically coupled to the substrate, and laterally adjacent both the sidewall of the first conductive portion and the sidewall of the second conductive portion the conductive region containing a channel region of the transistor;
• forming a source electrode within the conductive region wherein the sidewall of the first conductive portion forms a sidewall contact region to the source electrode;
• forming a drain electrode within the conductive region and laterally separated from the source electrode by the channel region, the sidewall of the second conductive portion forming a sidewall contact region to the drain electrode;
• and
• forming a gate electrode in close proximity to the channel region so that the gate electrode controls current flow through the channel region between the source electrode and the drain electrode.

A method for forming a field effect transistor comprising the steps of:

• providing a semiconductor substrate having a top surface;
• forming a first dielectric layer overlying the substrate;
• forming a conductive polysilicon layer overlying the first dielectric layer;
• forming a second dielectric layer overlying the conductive polysilicon layer;
• forming an opening through the first dielectric layer, the conductive polysilicon layer, and the second dielectric layer to expose a portion of the top surface of the substrate and segment the conductive polysilicon layer into a first and second regions of polysilicon material;
• epitaxially growing material from the portion of the top surface of the substrate to form a semiconductive region laterally adjacent both the first and second regions of polysilicon material;
• connecting the first and second regions of polysilicon material to the semiconductive region and diffusing dopants from the first and second regions of polysilicon material into the semiconductive region to form source and drain region separated by a channel region;
• thermally oxidizing a portion of the semiconductive region which overlies the channel region to form a gate dielectric;
• and
• forming a gate electrode overlying the gate dielectric.