Back to results
US 5,392,239 AGranted
Burst-mode DRAM
AssigneeS3 Incorporated
InventorsNeal D. Margulis, Takatoshi Ishii
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.
Claims10
A method for operating a storage device, the method comprising the steps of:
- applying a burst enable signal to the storage device;
- applying a first address signal to the storage device during a selected time, said first address signal indicating a row address in the storage device, said first address signal being applied by a row address strobe (RAS) signal applied to the storage device, wherein a burst mode is defined when the RAS signal is applied while the burst enable signal is applied;
- detecting the definition of the burst mode by sampling a state of the burst enable signal when the RAS signal is applied;
- applying a second address signal to the storage device, said second address signal indicating a column address in the storage device, said second address signal being applied by a column address strobe (CAS) signal applied to the storage device;
- and
- accessing the storage device according to the first and second address signals.
3 more elements
A method for operating a storage device, the method comprising the steps of:
- applying a burst enable signal to the storage device;
- applying a first address signal to the storage device during a selected time, said first address signal indicating a row address in the storage device, said first address signal being applied by a row address strobe (RAS) signal applied to the storage device, wherein a burst mode is defined when the RAS signal is applied while the burst enable signal is applied and a page mode is defined when the RAS signal is applied while the burst enable signal is disabled;
- applying a second address signal to the storage device, said second address signal indicating a column address in the storage device, said second address signal being applied by a column address strobe (CAS) signal applied to the storage device;
- and
- accessing the storage device according to the first and second address signals.
2 more elements
A method for accessing a storage device, said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns, the method comprising the steps of:
- receiving a first address along a set of address lines;
- receiving a second address along the address lines;
- generating at least one burst address based on the second address;
- applying the burst address to the storage device along a second set of address lines instead of the address lines;
- and
- accessing a storage location within the storage device indicated by the first address and the burst address.
3 more elements
A storage device comprising:
- a memory;
- first address lines for receiving a row address and a column address;
- a controller coupled to the address lines for generating at least one burst address based on the column address;
- second address lines coupled to the controller for receiving the burst address;
- and
- means coupled to the address and second address lines for accessing the memory according to the row address and the burst address.
3 more elements
In a memory circuit, a burst mode controller comprising:
- a signal detector for concurrently detecting a burst enable signal and a row address strobe signal (RAS) to define a burst mode;
- and
- means for incrementing an accessed column address when a column address strobe CAS signal is applied during the burst mode.
A storage device, comprising:
- a memory;
- means for receiving a burst enable signal;
- means for receiving a first address signal, said first address signal indicating a row address in the memory array, said first address signal being accompanied by a row address strobe (RAS) signal, wherein a burst mode is defined when the RAS signal is received while the burst enable signal is received;
- means for detecting the definition of the burst mode by sampling a state of the burst enable signal when the RAS signal is received;
- means for receiving a second address signal, said second address signal indicating a column address in the memory array, said second address signal being accompanied by a column address strobe (CAS) signal;
- and means for accessing the memory array according to the first and second address signals.
3 more elements
A storage device comprising:
- a memory;
- first address lines for receiving a row address and a column address;
- a controller coupled to the address lines for generating at least one burst address based on the column address, the controller comprising:
- a signal detector for concurrently detecting a burst enable signal and a row address strobe signal (RAS) to define a burst mode;
- and
- means for generating a burst address when a column address strobe CAS signal is applied during the burst mode;
- second address lines coupled to the controller for receiving the burst address;
- and
- means coupled to the first address and second address lines for accessing the memory according to the row address and the burst address.
6 more elements
Dependencies are inferred from the claim text.