Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions

In a data processor that executes a target instruction set including a predetermined number of instructions, an improved instruction processing system that facilitates processing instructions at a rate of more than one instruction per clock, said system comprising;

• an instruction fetch unit for fetching a plurality of instructions including a group of n, n being a predetermined integer, sequential instructions in a program where the number of possible groups that may be included in said plurality is the predetermined number raised to the nth power;
• a pipeline, having a series of pipeline stages and coupled to said instruction fetch unit, said pipeline having resources, such as registers and an ALU, capable of singly executing each instruction in said target instruction set and capable of executing in parallel only a limited subset of all the possible groups of instructions so that the n instructions included in one of the groups in said limited subset can be issued from said instruction fetch unit to said pipeline during a single clock and can be retired by said pipeline during a single clock, and with at least one of said groups in said limited subset including multiple non-branching instructions with one of said non-branching instructions being a memory reference type of instruction;
• a decoder, coupled to said instruction fetch unit and responsive to said fetched group of n instructions, for generating a plurality of decode result fields including status fields, each decode result field decoded from one of said instructions in a fetched group of n instructions and each status field indication resources required to execute a decoded instruction;
• a conflict check unit, coupled to said decoder and responsive to said status fields decoded from said fetched group of instructions, for determining whether the simultaneous execution of said fetched group of instructions will cause a resource conflict and for asserting a control signal if no resource conflict will occur;
• a grouping control unit, coupled to said decoder and to said pipeline and responsive to said control signal, for issuing said fetched group of n instructions to said pipeline during said single clock only if said control signal is asserted and said fetched group of instructions is one of said groups of instructions included in the limited subset of groups that can be executed in parallel;
• and
• an execution unit, coupled to said decoder and said pipeline and responsive to said decode result fields, for controlling said pipeline to process an issued group of instructions and to advance said issued group through said pipeline stages.