Workstation power management by page placement control
AssigneeInternational Business Machines Corporation
InventorColin G. Harrison
Life of this patent
Estimating the term…
Abstract
A power conserving method and apparatus for managing a computer memory. A first memory bank comprises normal RAM. A second memory bank comprises low-power RAM. More frequently used virtual pages are mapped onto the first memory bank while less frequently used virtual pages are mapped onto the second memory bank. Further power savings are achieved by removing power from the driver circuits of the memory controller for the second memory bank when the second memory bank is not being referenced.
Claims9
A method for managing a computer memory to conserve power, wherein the computer memory is divided into at least first and second memory banks, and a memory controller comprising a driver circuit section and a logic circuit section is operatively associated with the second memory bank, said method for managing a computer memory to conserve power comprising the steps of:
- counting references to a first page of memory in said second memory bank;
- calculating a reference frequency for said first page of memory;
- comparing said reference frequency to an established criterion;
- and
- transferring said first page of memory into said first memory bank if said reference frequency exceeds the established criterion;
- counting references to a plurality of pages of memory in said first memory bank;
- calculating a reference frequency for said plurality of pages of memory;.
- selecting a second page of memory from said plurality of pages based upon said reference frequency associated with said selected second page of memos;
- and
- transferring said second page of memory out of said first memory bank upon said transferring of said first page of memory into said first memory bank.
A low power consumption random access computer memory comprising:
- a multi-level volatile main memory device, including,
- a first main memory bank comprising a first page-oriented volatile random access memory (RAM), configured to store pages of virtual memory, and
- a second main memory bank comprising a second page-oriented volatile RAM which draws less power than said first page-oriented volatile RAM, said second page-oriented volatile RAM configured to store pages of virtual memory;
- a memory manager, electrically coupled to said first and second main memory banks, configured to manage the placement of said pages of memory, wherein more frequently referenced pages are placed in said first main memory bank;
- a private memory for storing page addresses;
- and
- a memory controller, electrically coupled to said second main memory bank and said private memory, said memory controller having a logic circuit and a driver circuit wherein said driver circuit is powerable separately from said logic circuit, and wherein said logic circuit detects address references to said second main memory bank, and thereafter, writes detected page addresses to said private memory.
A method for reducing power consumption in a page-oriented computer memory comprising a multi-level volatile memory device having a first main memory bank comprising first volatile random access memory (RAM) and configured to store pages of virtual memory, and a second main memory bank comprising second volatile RAM configured to store pages of virtual memory, the second volatile RAM drawing less power than the first volatile RAM, the method comprising steps of:
- determining reference frequencies for pages of the computer memory,
- maintaining, with a memory manager, more frequently referenced pages in the first main memory bank, wherein said more frequently referenced pages are identified based on said reference frequencies;
- maintaining, with said memory manager, less frequently referenced pages in the second main memory bank, wherein said less frequently referenced pages are identified based on said reference frequencies;
- controlling said memory with a memory controller comprising a logic part and a driver part, wherein the driver part is powerable independent from the logic part;
- switching off power to said driver part;
- and
- switching on power to said driver part when said logic part detects a reference to said second memory.
A low power consumption computer memory, comprising:
- a volatile computer main memory divided into at least first and second main memory banks, said first main memory bank comprising a first volatile random access memory (RAM) configured to store pages of virtual memory and said second main memory bank comprising a second volatile RAM configured to store pages of virtual memory;
- a memory controller including,
- a driver circuit electrically connected to said second main memory bank, said driver circuit configured for writing to and reading from said second main memory bank, and
- logic means for detecting an address reference to, and generating control signals and address data for, said second main memory bank;
- memory manager means, electrically connected to said first and second main memory banks, for managing placement of said pages of virtual memory according to a private memory map such that more frequently referenced pages are maintained in said first main memory bank;
- means for controlling power to said driver circuit independent of power to said logic means, whereby said driver circuit is operable in a first active state and a second unpowered state;
- generating means for generating a signal when said logic means detects an address reference to said second main memory bank;
- and
- receiving means for receiving said signal and accordingly instructing said driver circuit to switch to said first active state, said receiving means being electrically coupled to said generating means, whereby said second main memory bank may be referenced.
Dependencies are inferred from the claim text.