System including a data processor, a synchronous dram, a peripheral device, and a system clock

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to bits residing in the column address counter, accessing a set of columns for writing data bits from a data bus through an input circuit to the addressed row of storage cells in synchronism with the system clock signal;
• and
• e) transmitting a selected sequence of data bits from the data bus through the input circuit by clocking the column address counter in synchronism with the system clock signal and by applying bits from the column address counter to the input circuit for controlling transmission of the selected sequence of data bits through the input circuit from the data bus to the array of cells in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to the most significant bits residing in the column address counter, accessing a block of columns in the array of storage cells to read data bits from the addressed row of storage cells to an output multiplexer in synchronism with the system clock signal;
• and
• e) transmitting, in an order determined by the initial column address represented by the least significant bits of the initial column address, all of the bits of a set of data bits through the output multiplexer to a data bus in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to a most significant group of bits residing in the column address counter, accessing a block of columns in the array of storage cells to read data bits from the addressed row of storage cells to an output multiplexer in synchronism with the system clock signal;
• and
• e) transmitting a selected data bit through the output multiplexer by controlling a transmission path through the output multiplexer, in response to a least significant group of bits residing in the column address counter and applied to the output multiplexer in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) addressing a row of storage cells in an array of storage cells addressable by row address and column address;
• b) applying an initial column address to a column address counter;
• c) in response to a most significant group of bits residing in the column address counter, accessing a block of columns for writing a data bit from a data bus through an input multiplexer to the addressed row of storage cells;
• and
• d) transmitting a selected data bit through the input multiplexer by controlling a transmission path through the input multiplexer, in response to a least significant group of bits residing in the column address counter and applied to the input multiplexer.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to the initial column address, accessing a column to read data bits from the addressed row of storage cells to an output in synchronism with the system clock signal;
• and
• e) transmitting a selected sequence of data bits through the output to a data bus in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to the initial column address, accessing a column for writing data bits from a data bus to the addressed row of storage cells in synchronism with the system clock signal;
• and
• e) transmitting a selected sequence of data bits from the data bus to the array of storage cells in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to the bits residing in the column address counter, accessing a column in the array of storage cells to read data bits from the addressed row of storage cells to an output in synchronism with the system clock signal;
• and
• e) transmitting, in an order determined by the initial column address, all of the bits of a set of data bits to a data bus in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address counter;
• d) in response to the bits residing in the column address counter, accessing a column in the array of storage cells to read data bits from the addressed row of storage cells to an output in synchronism with the system clock signal;
• and
• e) transmitting a selected data bit through the output in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) addressing a row of storage cells in an array of storage cells addressable by row address and column address;
• b) applying an initial column address to a column address circuit;
• c) in response to a group of bits residing in the column address circuit, accessing a column for writing data bits from a data bus to the addressed row of storage cells;
• and
• d) transmitting selected data bits to the addressed row of storage cells by controlling a transmission path from the data bus, in response to a system clock signal.

A method for accessing a synchronous random access memory, the method comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with edges of the system clock signal;
• c) applying an initial column address to a column address circuit having an upper section and a lower section;
• d) in response to address bits residing in the upper section of the column address circuit, accessing a set of columns to read data bits from the addressed row of storage cells to an output circuit in synchronism with one of the edges of the system clock signal;
• and
• e) transmitting a selected sequence of data bits through the output circuit by clocking the column address circuit in synchronism with the one of the edges of the system clock signal and by applying the address bits from the lower section of the column address circuit to the output circuit for controlling transmission of the selected sequence of data bits through the output circuit to a data bus in synchronism with the one of the edges of the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with edges of the system clock signal;
• c) applying an initial column address to a column address circuit having an upper section and a lower section;
• d) in response to address bits residing in the upper section of the column address circuit, accessing a set of columns for writing data bits from a data bus through an input circuit to the addressed row of storage cells in synchronism with one of the edges of the system clock signal;
• and
• e) transmitting a selected sequence of data bits from the data bus through the input circuit by clocking the column address circuit in synchronism with the edges of the system clock signal and by applying address bits from the lower section of the column address circuit to the input circuit for controlling transmission of the selected sequence of data bits through the input circuit from the data bus to the array of cells in synchronism with the edges of the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with edges of the system clock signal;
• c) applying an initial column address to a column address circuit;
• d) in response to the most significant bits residing in the column address circuit, accessing a group of columns in the array of storage cells from which to read data bits from the addressed row of storage cells to an output circuit in synchronism with one of the edges of the system clock signal;
• and
• e) transmitting, in an order determined by a portion of the initial column address, all of the bits of a set of data bits through the output circuit to a data bus in synchronism with the edges of the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) applying a system clock signal to the synchronous random access memory;
• b) addressing a row of storage cells in an array of storage cells addressable by row address and column address in synchronism with the system clock signal;
• c) applying an initial column address to a column address circuit having upper and lower sections;
• d) in response to a group of bits residing in the upper section of the column address circuit, accessing a set of columns in the array of storage cells to read data bits from the addressed row of storage cells to an output circuit in synchronism with the system clock signal;
• and
• e) transmitting a selected data bit through the output circuit by controlling a transmission path through the output circuit, in response to a group of bits residing in a lower section of the column address circuit and applied to the output circuit in synchronism with the system clock signal.

A method for accessing a synchronous random access memory comprising the steps of:

• a) addressing a row of storage cells in an array of storage cells addressable by row address and column address;
• b) applying an initial column address to a column address circuit having upper and lower sections;
• c) in response to a group of bits residing in the upper section of the column address circuit, accessing a set of columns for writing a data bit from a data bus through an input circuit to the addressed row of storage cells;
• and
• d) transmitting a selected data bit through the input circuit by controlling a transmission path through the input circuit, in response to a group of bits residing in the lower section of the column address circuit and applied to the input circuit.

A method for reading data bits from a memory device having a data output terminal, the method comprising the steps of:

• receiving a system clock signal;
• activating a row address enabling signal for activating a first word line of an array in synchronism with the system clock signal;
• applying a first column address to the array for selecting a first plurality of data bits;
• deactivating the row address enabling signal;
• activating the row address enabling signal for activating a second word line of the array in synchronism with the system clock signal;
• applying a second column address to the array for selecting a second plurality of data bits;
• and
• sequentially transmitting the data bits of the first and second pluralities of data bits to the data output terminal in synchronism with the system clock signal, at least one data bit being transmitted to the output terminal per system clock cycle while the first and second pluralities of data bits are being transmitted.

A method for reading data bits from a memory device having a data output terminal, the method comprising the steps of:

• receiving a system clock signal;
• activating an address enabling signal for activating a first word line in an array and for selecting a first plurality of data bits from the array in synchronism with the system clock signal;
• deactivating the address enabling signal;
• activating the address enabling signal for activating a second word line in the array and for selecting a second plurality of data bits from the array in synchronism with the system clock signal;
• and
• sequentially transmitting the data bits of the first and second pluralities of data bits to the data output terminal in synchronism with the system clock signal, at least one data bit being transmitted to the output terminal per system clock cycle while the first and second pluralities of data bits are being transmitted.