Resonance tunnel diode memory

A semiconductor memory device comprising:

• a plurality of bit lines;
• a plurality of word lines which intersect the plurality of bit lines to form a matrix of cross points, each cross point corresponding to an intersection between a respective bit line and respective word line;
• a plurality of memory cells, a respective memory cell disposed at each cross point and corresponding to the respective word line and respective bit line intersecting at the respective cross point, each memory cell being individually selectable in accordance with voltages on the corresponding bit line and the corresponding word line, each memory cell comprising:
• a transfer gate having a first current terminal connected to the corresponding bit line, a control terminal connected to the corresponding word line, and a second current terminal, and
• a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween which is connected to the second current terminal of the transfer gate;
• and
• a characteristic controlling circuit which is coupled to the plurality of bit lines and controls the voltage of each bit line based on whether a respective memory cell corresponding to the respective bit line is selected or not selected, the characteristic controlling circuit comprising a plurality of negative differential resistance elements respectively corresponding to, and connected to, the plurality of bit lines.