Complementary analog multiplier circuits with differential ground referenced outputs and switching capability

A complementary multiplier for generating a product signal from two input signals, said multiplier comprising:

• a first input amplifier having a pair of inputs and first and second pairs of outputs, for generating first and second pairs of currents at said first and second pairs of outputs from a first input signal applied between said pair of inputs, said first and second pairs of currents having opposite polarities;
• a first pair of transistors, each having a collector, a base coupled to AC ground, and an emitter coupled to one of said first pair of outputs of said first input amplifier, for generating first and second intermediate signals from said first pair of currents;
• a second pair of transistors complementary to said first pair of transistors, each having a base coupled to AC ground, a collector connected to the collector of one of said first pair of transistors, and an emitter coupled to one of said second pair of outputs of said first input amplifier, for generating third and fourth intermediate signals from said second pair of currents;
• a second input amplifier having a pair of inputs and first and second outputs for generating a third pair of currents at said first and second outputs from a second input signal applied between said pair of inputs, said third pair of currents having opposite polarities;
• a first gain core differential amplifier having first and second input terminals for receiving said first and second intermediate signals, respectively, first and second output terminals corresponding to said first and second input terminals, and a third input terminal for controlling the transconductance of said first gain core differential amplifier with one of said third pair of currents;
• a second gain core differential amplifier complimentary to said first gain core differential amplifier, having first and second input terminals for receiving said third and fourth intermediate signals, respectively, first and second output terminals corresponding to said first and second input terminals, and a third input terminal for controlling the transconductance of said differential amplifier with the other of said third pair of currents, said first and second outputs of said second gain control differential amplifier being connected to said first and second outputs, respectively, of said first gain control amplifier to form first and second multiplier outputs, said first and second gain core differential amplifiers each having gain characteristics substantially matching those of said first and second pairs of transistors, respectively, for generating output signals having equal magnitudes and opposite polarities at said first and second multiplier outputs.

A differential amplifier input stage for generating balanced differential output signals suitable for driving complementary, differential stages, said input stage comprising:

• an input amplifier having a pair of inputs and first and second pairs of outputs for generating first and second pairs of currents at said first and second pairs of outputs from a first input signal applied between said pair of inputs, said first and second pairs of currents having opposite polarities;
• a first pair of transistors, each transistor of said first pair of transistors having a collector, a base coupled to AC ground, and an emitter coupled to one of said first pair of outputs of said first input amplifier, for generating first and second intermediate signals at the emitters of said first pair of transistors from said first pair of currents, the emitters of said first pair of transistors forming a first differential output of the differential amplifier input stage, for providing a first differential output signal equal to the difference between said first and second intermediate signals;
• a second pair of transistors complementary to said first pair of transistors, each transistor of said second pair of transistors having a base coupled to AC ground, a collector connected to the collector of one of said first pair of transistors, and an emitter coupled to one of said second pair of outputs of said first input amplifier, for generating third and fourth intermediate signals at the emitters of said second pair of transistors from said second pair of currents, the emitters of said second pair of transistors forming a second differential output of the differential amplifier input stage, for providing a second differential output signal equal to the difference between said third and fourth intermediate signals said first differential output signal being equal to said second differential output signal.