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AssigneeMicroelectronics and Computer Technology Corporation
InventorsUttam S. Ghoshal, Harry Kroger
Estimating the term…
Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and semiconducting circuits, with at least some superconducting circuitry used, to write and read information. The state of memory cells in the hybrid memories is determined by utilizing superconductor current sensing schemes to detect currents in the bit-line, thereby avoiding any bit-line charging delays and other problems associated with purely semiconductor memories. Additional features of the superconducting-semiconducting hybrid memories include wide margins, dense packing of memory cells, low power dissipation and fast access times. Interface curcuitry for converting superconducting signals to signals compatible with semiconductor circuits and for converting semiconductor signals to signals compatible with superconducting circuits is also disclosed.
A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising:
A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising:
A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising:
A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising:
A method of accessing from a memory cell having at least a first terminal and a second terminal information in binary forms of the type useful in computer or logic circuit applications, wherein a matrix comprised of a plurality of memory cells of common design is formed in a row and column format, with rows being addressed via word lines, wherein each word line is connected to said first terminal of each memory cell in said row, and columns being addressed via bit-lines, wherein a superconducting current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output, is connected through said bias input to at least one bit-line and is connected to said second terminal of each memory cell in said column associated with at lest one bit-line, comprising the steps of:
A method of accessing from a memory cell having at least a first terminal and a second terminal information in binary forms of the type useful in computer or logic circuit applications, wherein a matrix comprised of a plurality of memory cells of common design is formed in a row and column format, with rows being addressed via word lines, wherein each word line is connected to said first terminal of each memory cell in said row, and columns being addressed via bit-lines, wherein a superconducting current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output, is connected through said bias input to at least one bit-line and is connected to said second terminal of each memory cell in said column associated with at lest one bit-line, comprising the steps of:
Dependencies are inferred from the claim text.