Video multiplexing system for superimposition of scalable video streams upon a background video data stream

An apparatus for processing image signals, for use in a computer system having a CPU, a CPU bus connected to said CPU, a display controller, and a display device comprising:

• a video memory for memorizing a given digital image signal
• first write control means, connected to said CPU bus, for controlling the writing of said given digital image signal in said video memory by supplying a first write address to said video memory, a range of said first write address being specified with a plurality of write address parameters set by said CPU;
• a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals;
• first read control means, connected to said CPU bus, for supplying said video switch with a first selection signal indicating to select one of said plurality of image signals, and controlling the reading of said first image signal out of said video memory by supplying a first read address to said video memory in synchronism with a first horizontal synchronizing signal and a first vertical synchronizing signal which are supplied from said display controller, a range of said first read address being specified with a plurality of read address parameters set by said CPU;
• second selection means, connected to said video memory, for selecting one of a plurality of digital image signals to supply the selected digital image signal to said video memory;
• address selection means, connected to said first write control means and said video memory, for selecting one of a plurality of write addresses including said first write address supplied from said first write control means;
• and
• second write control means, connected to said CPU bus, for receiving a first image signal from said CPU through said CPU bus, supplying said first image signal as one of said plurality of digital image signals to said second selection means, supplying a second write address for said first image signal as one of said plurality of write addresses to said address selection means, supplying a second selection signal to said second selection means to instruct said selecting in said second selection means, and supplying a third selection signal to said address selection means to instruct said selecting in said address selection means.

An apparatus for processing image signals, for use in a computer system having a CPU, a CPU bus connected to said CPU, a display controller, and a display device, comprising:

• a video memory for memorizing a given digital image signal;
• first write control means, connected to said CPU bus, for controlling the writing of said given digital image signal in said video memory by supplying a first write address to said video memory, a range of said first write address being specified with a plurality of write address parameters set by said CPU;
• a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said Plurality of image signals;
• and
• first read control means, connected to said CPU bus, for supplying said video switch with a first selection signal indicating to select one of said plurality of image signals, and controlling the reading of said first image signal out of said video memory by supplying a first read address to said video memory in synchronism with a first horizontal synchronizing signal and a first vertical synchronizing signal which are supplied from said display controller, a range of said first read address being specified with a plurality of read address parameters set by said CPU.
• wherein said first read control means includes:
• means for generating a first clock signal on the basis of said plurality of read address parameters and said first horizontal synchronizing signal, and supplying said first clock signal to said video memory, said first clock signal regulating increment of a horizontal read address of said video memory, said clock signal having a frequency which has a value of a frequency of said first horizontal synchronizing signal multiplied by a first integer included in said plurality of read address parameters, whereby a horizontal size of a second image represented by said first image signal read out from said video memory is changeable by changing said third integer.