Digital signal processor for use in sound quality treatment by filtering

A digital signal processing device comprising:

• data buffer memory means for storing data to be changed transmitted from a control device;
• first address counter means for specifying a first address in said data buffer memory means;
• second address counter means for receiving a change start address of the data from said control device, and then producing a data write address;
• internal memory means for storing the data;
• pointer means for specifying a second address in said internal memory means;
• address comparator means for comparing the change start address from said second address counter means with the second address from said pointer means, and, when these addresses coincide with each other, bringing said internal memory means in a write enable state;
• and
• transfer means for transferring the data to be changed in said data buffer memory means to said internal memory means when said address comparator means has brought said internal memory means in the write enable state.

A digital signal processor operated under control of a program, comprising:

• an internal memory in which first data are stored;
• a register connected to said internal memory and which receives said first data;
• a logic circuit connected to said register, said logic circuit receiving said first data from said register and performing predetermined functions using said first data;
• a data buffer memory in which second data used to replace selected ones of said first data are stored;
• a write start address counter containing a write start address of said second data;
• a pointer containing a current address of said internal memory;
• a comparator connected to pointer and said write start address counter for comparing said current address with said write start address;
• a control device for controlling transfer of said second data into said buffer memory;
• and
• means for simultaneously writing said second data into said internal memory and transferring said second data into said register when said current address and said write start address are determined to coincide using said comparator.