Floating point data processor and a method for performing a floating point square root operation within the data processor

A data processor for calculating a square root of a number, the data processor comprising:

• an execution device for processing data within the data processor;
• means for approximating an inverse square root of the number coupled to the execution device;
• a memory device which stores a first binary value and a second binary value wherein the first binary value, when decoded by the execution device, indicates that a square root operation is to be performed on the second binary value;
• and
• means for processing the square root operation coupled to the execution device, the means for processing receiving an inverse square root approximation from the means for approximating an inverse square root approximation, providing a more accurate inverse square root approximation from the inverse square root approximation, using the more accurate inverse square root approximation and the number to create an exact floating point value and a small floating point value wherein the sum of the exact floating point value and the small floating point value is a substantially close approximation to the actual square root of the number, and selectively adding a constant value to a least significant bit position of the substantially close approximation in order to more accurately represent the actual square root of the number.

A data processing system for performing floating point operations, the data processing system being coupled to an external memory device, the data processing system comprising:

• a memory storage array within the data processing system for storing data within the data processing system;
• a control unit coupled to the memory storage array and coupled to the external memory device, the control unit processing data and computer instructions stored in the memory storage array and the external memory device, the control unit selectively reading the data and the computer instructions from the memory storage array and generating control signals and providing floating point data for use within the data processing system;
• a floating point execution unit coupled to the control unit for receiving the floating point data and control signals, the floating point execution unit being capable of performing floating point mathematical operations using the floating point data, the floating point unit generating a first floating point value in response to the receipt of at least one of the control signals, the first floating point value being an adjusted approximate inverse square root of the floating point data, the floating point execution unit performing a sequence of operations to improve the precision of the first floating point value, the floating point execution unit using the first floating point value to generate a second floating point value which is an exact floating point number and a third floating point number which is significantly less than the second floating point number wherein the addition of the second floating point number and the third floating point number provides a P-bit accurate square root approximation to the floating point data wherein P is a number of significant floating point bit positions available within the data processing system, the floating point execution unit providing the P-bit accurate square root approximation as a square root value output to the control unit.

A method for performing a floating point operation in a data processing system, the data processing system having a control unit, a means for storing data coupled to the control unit, and a floating point execution unit coupled to the control unit, the method comprising:

• reading, by the control unit, a computer operation and a data operand from the means for storing data;
• decoding the computer operand, by the control unit, to determine that the floating point execution unit is to be accessed in order to perform the computer operation, the computer operation being a square root operation;
• transmitting at least one control signal and the data operand from the control unit to the floating point exception unit;
• providing, by the floating point execution unit in response to the at least one control signal, a first floating point value wherein the first floating point value is an adjusted approximation of an inverse square root of the data operand wherein the data operand has a precise mathematical square root;
• iterating, at least once, through a plurality of floating point operations within the floating point execution unit, the plurality of floating point operations being used to improve the precision of the first floating point value until a predetermined precision of the first floating point value is achieved;
• generating from the first floating point value a first value and a second value, the first value being an exact floating point value which is represented in P bits with no loss of significant bits wherein P is a finite integer greater than zero and is the number of floating point bits used within the data processing to represent floating point values, the second value being a small floating point value which is significantly less than the exact floating point value;
• adding the exact floating point value and the small floating point value together within the floating point execution unit to form an accurate approximate square root of the data operand;
• performing a calculation within the floating point execution unit to determine whether the accurate approximate square root needs to be numerically adjusted;
• and
• selectively adjusting the accurate approximate square root in the floating point execution unit by selectively adding a constant to at least a least significant bit position of the accurate approximate square root to numerically adjust the accurate approximate square root.

A method for performing a floating point operation within a data processing system, the data processing system having a central processing unit, a storage device, and circuitry for processing floating point operations, the method comprising:

• transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus, the number having a floating point representation within the data processing system;
• determining, by a decoding process in the central processing unit, that the data processing system is requesting that the square root of the number be calculated;
• transmitting the number from the central processing unit to the circuitry for processing floating point operations;
• generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation;
• providing an exact component value via the circuitry for processing floating point operations, the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation;
• providing, via the circuitry for processing floating point operations, a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value, the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum;
• generating a trial value using the circuitry for processing floating point operations, the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits;
• and
• selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system.

A method for performing a floating point operation within a data processing system, the data processing system having a central processing unit, a means for storing data, and circuitry for processing floating point operations, the method comprising:

• transmitting a number having an exact mathematical square root from the means for storing data to the central processing unit via a data bus, the number having a floating point representation within the data processing system;
• determining, by a decoding process in the central processing unit, that the data processing system is requesting that the square root of the number be calculated;
• transmitting the number from the central processing unit to the circuitry for processing floating point operations;
• generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root number has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation;
• using the circuitry for processing floating point operations to provide an exact component value from the number and the approximate inverse square root value wherein the exact component value has a precise representation in the floating point representation and is stored in the means for storing data;
• using the circuitry for processing floating point operations to provide a small component value from the number and the approximate inverse square root value wherein the small component value is significantly less than the exact component value and is stored in the means for storing data, the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum;
• adding the exact component value to the small component value via the circuitry for processing floating point operations to provide a trial value, the trial value being altered to be representable in P bits;
• determining in the circuitry for processing floating point operations whether the trial value or a modified trial value is a more accurate square root of the number wherein the modified trial value is the trial value added to a logic value wherein the logic value is a value selected from the group consisting of:
• -1 and 1;
• and
• selecting either the trial value or the modified trial value as the square root of the number and providing the square root of the number as an output of the circuitry for processing floating point operations.

A method for providing a square root, in a data processor, of a number having an exact square root, the method comprising the steps of:

• transmitting, via a hardware bus, at least one control signal and a data value from a control unit of the data processor to a floating point processor portion of the data processor, the control signal being asserted if the floating point processor portion is to find the square root of the number;
• generating an approximate inverse square root number within the floating point processor portion wherein the approximate inverse square root number does not exactly equal an inverse of the exact square root of the number, the data processor being able to represent the square root in P hardware bits of precision within the floating point processor portion where P is a finite integer greater than zero;
• processing the approximate inverse square root number to generate an exact component value within the floating point processor portion, wherein the exact component value has Q hardware significant bits and may be represented in P bits with no loss of significant bits because Q .ltoreq.P;
• processing the approximate inverse square root number to generate a small component value from the approximate inverse square root number wherein the small component value is significantly less than the exact component value;
• adding the exact component value and the small component value within the floating point processor portion to provide a trial value wherein the trial value is altered to be representable in P bits;
• and
• selecting either the trial value or the trial value plus a constant as the square root of the number.

A method for generating a calculated square root of a number having a mathematically exact square root within a data processor, the data processor having an execution control portion, a data storage portion, and a floating point computational portion, the method comprising the steps of:

• reading a number, via a data bus, from the data storage portion to the execution control portion;
• determining, by the execution control portion, that the number read from the data storage portion is to be processed so that the number's square root is calculated;
• transmitting the number from the execution control portion to the floating point computational portion;
• iteratively generating an approximate inverse square root for the number within the floating point computational portion, the approximate inverse square root becoming closer to the mathematically exact inverse square root with each iteration until a predetermined precision tolerance of the approximate inverse square root is achieved, the approximate inverse square root which satisfies the predetermined precision tolerance does not exactly equal the mathematically exact inverse square root of the number, the floating point computational portion being able to represent the approximate inverse square root and the calculated square root in P hardware bits of precision where P is a finite integer greater than zero;
• calculating, using the floating point computational portion, an exact component value from the approximate inverse square root wherein the exact component value may be represented in P bits with no loss of significant bits;
• calculating, using the floating point computational portion, a small component value from the approximate inverse square root number wherein the small component value is significantly less than the exact component value;
• generating a trial value within the floating point computational portion by adding the exact component value and the small component value wherein the trial value is either truncated or rounded to be representable in P bits;
• and
• selecting either the trial value or the trial value plus a logic one least significant bit of the trial value as the square root of the number.

A method for generating a square root of a number having an exact mathematical square root, the generating being performed via an execution device having a control unit, a memory device, and a floating point unit, the square root being represented via a floating point representation, the method comprising the steps of:

• determining, via the control unit and data stored within the memory unit, that the square root of the number is to be generated by the execution device;
• providing an approximate adjusted inverse square root number to the execution device from the floating point unit wherein the approximate adjusted inverse square root number has more than P/2 bits of precision where P is a finite integer greater than zero and is the number of significant bits in the floating point representation;
• calculating, using the floating point unit, an exact component value from the number and the approximate adjusted inverse square root value wherein the exact component value has a precise representation in the floating point representation;
• calculating, using the floating point unit, a small component value from the number and the approximate adjusted inverse square root value wherein the small component value is significantly less than the exact component value, the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum;
• calculating, using the floating point unit, a trial value by adding the exact component value and the small component value wherein the trial value is altered to be representable in P bits;
• and
• selecting one of either the trial value or the trial value plus a constant as the square root of the number.

A data processor for calculating a square root of a number, the data processor comprising:

• an execution device for processing data within the data processor;
• means for approximating an inverse square root of the number coupled to the execution device;
• a memory device which stores a first binary value and a second binary value wherein the first binary value, when decoded by the execution device, indicates that a square root operation is to be performed on the second binary value;
• and
• means for processing the square root operation coupled to the execution device, the means for processing receiving an inverse square root approximation from the means for approximating an inverse square root approximation, iteratively providing a more accurate inverse square root approximation from the inverse square root approximation, using the more accurate inverse square root approximation and the number to create both an exact floating point value and a small floating point value wherein the sum of the exact floating point value and the small floating point value is a substantially close approximation to the actual square root of the number.