Multimedia storage system with highly compact memory device

The vertical memory cell formed in a substrate comprising:

• a buried source region;
• a drain region;
• a channel region formed between said buried source region and said drain region;
• a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region;
• and
• a control gate insulated from said floating gate,
• wherein said drain region includes an extended drain region formed from polysilicon.

A vertical memory cell formed in a substrate comprising:

• a buried source region;
• a drain region;
• a channel region formed between said buried source region and said drain region;
• a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region;
• a control gate insulated from said floating gate;
• and
• an erase/program gate positioned between said drain region and said control gate and in operative relation to said floating gate, wherein said cell is programmed by electrons tunneling from said erase/program gate to said floating gate and erased by electrons tunneling from said floating gate to said erase/program gate.

A vertical memory cell formed in a substrate comprising:

• a buried source region;
• a drain region;
• a channel region formed between said buried source region and said drain region;
• a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region;
• and
• a control gate insulated from said floating gate;
• and
• an erase/program gate positioned between said drain region and said control gate and in operative relation to said floating gate, wherein said erase/program gate is positioned above said drain region.

A vertical memory cell formed in a substrate comprising:

• a floating gate transistor formed in a first trench in said substrate;
• a series transistor formed in a second trench in said substrate, said second trench vertically aligned with said first trench;
• a buried source region;
• a drain region;
• a channel region formed between said buried source region and said drain region;
• a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region;
• and
• a control gate insulated from said floating gate,
• wherein said first and second transistors share said channel region, and wherein said floating gate is formed in said first trench.