Short channel MOSFET with buried anti-punch through region

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein:

• said transistor comprises;
• an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and resistivity and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that
• (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region (12) and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region;
• (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region said source region;
• (c) an effective channel length of less than 1 .mu.m is defined by the distance between said source and said drain regions;
• (d) said gate insulator layer is less than 500 .ANG.,
• (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region.

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein:

• said transistor comprises:
• an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region formed with an inversion region and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that
• (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region;
• (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length including beneath said drain region, but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region;
• (c) an effective channel length of less than 1 .mu.m is defined by the distance between said source and said drain regions;
• (d) said gate insulator layer is less than 500 .ANG., and
• (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region,
• said one storage capacitor comprising an inversion region serving as a drain region and an insulator layer and an electrode formed above said inversion region.

A semiconductor device having a complementary inverter circuit comprising an n-channel insulated-gate transistor and a p-channel insulated-gate transistor connected in series to said n-channel insulated-gate transistor, gates of these transistors being directly connected to each other, wherein:

• each of these transistors has a semiconductor substrate, and having, closer to a surface of said substrate, a source of semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and a low resistivity and a channel semiconductor region of the opposite type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that
• (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is a metal, a metal silicide, or a highly-doped polysilicon of conductivity type opposite to that of said source region;
• (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region;
• (c) an effective channel length of less than 1 .mu.m is defined by the distance between said source and said drain regions;
• (d) said gate insulator layer is less than 500 .ANG., and
• (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region,
• said one storage capacitor comprising an inversion region serving as a drain region and an insulator layer and an electrode formed above said inversion region.