Dynamic flow instruction cache memory organized around trace segments independent of virtual address line
AssigneeIntel Corporation
InventorsAlexander Peleg, Uri Weiser
Life of this patent
Estimating the term…
Abstract
An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory may cross virtual address line boundaries. Branch prediction is integrally incorporated into the cache array permitting the crossing of branch boundaries with a single access.
Claims19
A method of loading computer program instructions into a cache memory, said cache memory being organized by addressable lines, comprising the steps of:
- identifying basic blocks of computer program instructions such that a first instruction in each of said blocks follows a branch instruction and a last instruction in each of said blocks is a branch instruction;
- identifying a trace segment of a running computer program comprising a sequence of said basic blocks that are executed consecutively;
- and
- organizing storage in said cache memory by loading more than one of said basic blocks in at least one line of said cache memory in the sequence that said basic blocks occurred in said trace segment such that when the first basic block in said one line is addressed, the remaining basic blocks in said line are accessed independent of virtual address line boundaries.
In a computer system that supports speculative execution of instructions, said computer system comprising a cache memory having a plurality of lines, a main memory, and a CPU that reads a static sequence of addressable instructions from said main memory, a method of storing instructions in the cache memory, said cache memory being organized by lines, comprising the steps of:
- running a computer program so as to find committed instructions fetched from said main memory in their order of execution, said order crossing virtual address boundaries;
- identifying basic blocks of said committed instructions that will be unconditionally executed in sequential order,
- loading only basic blocks into said lines of said cache memory after said committed instructions are unconditionally executed;
- organizing storage in said cache memory by loading more than one of said basic blocks in at least one line of said cache memory so that all of the loaded basic blocks are fetched from the one line of cache memory with a single access;
- and
- associating each of said lines of cache memory by storing at least one of the basic blocks with a memory address of the first of said committed instructions in said one of the basic blocks.
Dependencies are inferred from the claim text.