Process and device for the decoding of a shortened, cyclic binary code using error correction

A method of decoding a shortened cyclic binary code, for correcting a single error burst b(x) of a length t or shorter said cyclic binary code having generator polynomial of type g(x)=(x.sup.2t-1 +1).p(x), wherein p(x) is a prime polynomial over GF(2) and with period ro, where .GAMMA.2 equal to (ro-h) is calculated by cyclic shifting in a shift register, with h equal to a number of shifting operations required to obtain the single error burst b(x) in t least significant positions of a syndrome polynomial s2(x), said method comprising the steps of:

• calculating (n-q) wherein:
• (n-q)=.GAMMA.2+1-ro;
• and
• correcting the single error burst in a correcting circuit by adding modulo 2 a polynomial (x.sup.n-q).b(x) to a received vector.

A decoding device for a shortened cyclic binary code having a generator polynomial of type

• g(x)=(x.sup.2t-1 +1).p(x)
• where p(x) is a prime polynomial over GF(2) with period ro, satisfying ro>(n-b) where n equals a length of a binary code and b equals a number of shortened bits for correcting single error bursts of a given length t and comprising:
• input means for receiving a code word (r(X));
• a first unidirectional shift register, with (2t-1) stages, serially connected to said input means;
• a second unidirectional shift register, with m stages, serially connected to said input means, said first and second unidirectional shift registers receiving as input the code word (r(X));
• a test for zero circuit, parallely connected to (t-1) highest order stages of said first unidirectional shift register;
• first modulo (2t-1) counting means, for computing a number of shifting operations performed by said first unidirectional shift register;
• a third unidirectional shift register with m stages, parallely connected with said second unidirectional shift register for shifting data in a direction opposite to said first and second unidirectional shift registers;
• a comparing device, parallely connected between the t lowest order stages of said first unidirectional shift register and said third unidirectional shift register, wherein an output of said comparing device is provided to second modulo ro counting means for computing a number of shifting operations performed by said second unidirectional shift register;
• and
• a computing circuit connected to outputs of said first modulo (2t-1) and second modulo ro counting means for correcting the single error burst in the code word (r(X)).

A decoding device for a shortened cyclic binary code having a generator polynomial of type

• g(x)=(x.sup.2t-1 +1).p(x)
• where p(x) is a prime polynomial over GF(2) with period ro, satisfying ro>(n-b) where n equals a length of binary code and b equals a number of shortened bits for correcting single error bursts of a given length t or shorter, comprising:
• input means for receiving a code word (r(X));
• a first unidirectional shift register with (2t-1) stages, serially connected to said input means;
• a second bidirectional shift register, with m stage, serially connected to said input means, said first and second shift registers receiving as input the code word (r(X));
• a test for zero circuit parallely connected to (t-1) highest order stages of said first unidirectional shift register;
• first modulo (2t-1) counting means for computing a number of shifting operations performed by said first unidirectional shift register;
• a comparing device parallely connected between the t lowest order stages of said first unidirectional shift register and said second bidirectional shift register, where an output of said comparing device is provided to second modulo ro counting means for computing a number of shifting operations performed by said second bidirectional shift register;
• and
• a computing circuit connected to outputs of said first modulo (2t-1) and second modulo ro counting means for correcting the single error burst in the code word (r(X)).