Fully differential line driver circuit having common-mode feedback

A CMOS differential line driver circuit, comprising:

• an input differential amplifier having first and second input terminals for receiving differential input signals, and first and second output terminals for providing first and second intermediate differential signals;
• a first differential amplifier having first and second input terminals coupled to the first and second output terminals of the input differential amplifier, and having first and second output terminals for providing third and fourth intermediate signals;
• a first common-mode control circuit having first and second input terminals coupled to the first and second input terminals of the first differential amplifier, respectively, for sensing a common-mode voltage of the first and second intermediate signals, and controlling a common-mode voltage of the third and fourth intermediate signals;
• a second differential amplifier having first and second input terminals coupled to the first and second output terminals of the input differential amplifier, and having output terminals for providing fifth and sixth intermediate signals;
• a second common-mode control circuit having first and second input terminals coupled to the first and second input terminals of the second differential amplifier, respectively, for sensing the common-mode voltage of the first and second intermediate Signals, and controlling a common-mode voltage of the fifth and sixth intermediate signals;
• a first output driver stage having first and second transistors coupled in series for receiving the third intermediate signal and the fifth intermediate signal, and for providing a first output signal at a first output node between the first and second transistors;
• a second output driver stage having third and fourth transistors coupled in series for receiving the fourth intermediate signal and the sixth intermediate signal, and for providing a second output signal at a second output node between the third and fourth transistors;
• and
• a common-mode feedback circuit, coupled to the first and second output nodes and to the input differential amplifier, for sensing a common-mode voltage of the first and second output signals, and providing a common-mode feedback voltage to control the common-mode voltage of the first and second intermediate signals.

A fully differential line driver circuit, comprising:

• a high gain input amplifier stage having first and second input terminals for receiving first and second input signals, respectively, and first and second output terminals for providing first and second intermediate differential signals;
• a first differential amplifier, comprising:
• a first P-channel transistor having a source connected to a first power supply voltage terminal, a gate, and a drain;
• a second P-channel transistor having a source connected to the first power supply voltage terminal, a gate connected to the gate of the first P-channel transistor, and a drain;
• a first N-channel transistor having a drain connected to the drain of the first P-channel transistor, a gate connected to the first output terminal of the high gain input amplifier stage, and a source;
• a second N-channel transistor having a drain connected to the drain of the second P-channel transistor, a gate connected to the second output terminal of the high gain input amplifier stage, and a source connected to the source of the first N-channel transistor;
• and
• a first current source having a first terminal connected to the sources of the first and second N-channel transistors, and a second terminal connected to a second power supply voltage terminal;
• a second differential amplifier comprising:
• a third N-channel transistor having a source connected to the second power supply voltage terminal, a gate, and a drain;
• a fourth N-channel transistor having a source connected to the second power supply voltage terminal, a gate connected to the gate of the third N-channel transistor, and a drain;
• a third P-channel transistor having a drain connected to the drain of the third N-channel transistor, a gate connected to the first output terminal of the high gain input amplifier stage, and a source;
• a fourth P-channel transistor having a drain connected to the drain of the fourth N-channel transistor, a gate connected to the second output terminal of the high gain input amplifier stage, and a source connected to the source of the third P-channel transistor;
• and
• a second current source having a first terminal connected to the first power supply voltage terminal, and a second terminal connected to the sources of the third and fourth P-channel transistors;
• a first output stage, comprising:
• a fifth P-channel transistor having a source connected to the first power supply voltage terminal, a gate connected to the drain of the first P-channel transistor, and a drain for providing a first output signal;
• and
• a fifth N-channel transistor having a drain connected to the drain of the fifth P-channel transistor, a gate connected to the drain of the third P-channel transistor, and a source connected to the second power supply voltage terminal;
• and
• a second output stage, comprising:
• a sixth P-channel transistor having a source connected to the first power supply voltage terminal, a gate connected to the drain of the second P-channel transistor, and a drain for providing a second output signal;
• and
• a sixth N-channel transistor having a drain connected to the drain of the sixth P-channel transistor, a gate connected to the drain of the fourth P-channel transistor, and a source connected to the second power supply voltage terminal.