Phase lock loop with self test circuitry and method for using the same

A method for self test of a phase lock loop, the phase lock loop receiving a reference signal of a first frequency and producing an output signal of a second frequency, the second frequency being some multiple of the first frequency, the method comprising:

• forming a pulse of a predetermined period from the input signal of the first frequency, said predetermined period being significantly larger than the period of the second frequency produced by the phase lock loop;
• coupling said pulse and the output signal of the phase lock loop to an And gate thereby producing a series of pulses of the second frequency for said predetermined period of said pulse;
• counting said series of pulses with a counter circuit;
• and
• comparing a count of said string of pulses to an expected count of pulses.

An integrated circuit with self test comprising:

• a phase lock loop including an input for receiving an input signal of a first frequency and an output for providing an output signal of a second frequency;
• a pulse circuit including an input for receiving said input signal of said first frequency and an output for providing a pulse of a predetermined period, said predetermined period being a multiple of the period of said output signal of said phase lock loop;
• an And gate including an input coupled to said output of said phase lock loop, an input coupled to said output of said pulse circuit, and an output, said And gate providing a series of pulses of said second frequency during said predetermined period of said pulse;
• and
• a counter circuit including an input coupled to said output of said And gate and a plurality of outputs for providing a count of said series of pulses, said count being compared with an expected count to determine accuracy of said phase lock loop.