ECL test access port with low power control

An integrated circuit device ECL test access port (TAP) having dedicated TAP access pins and associated pin electronics including a TAP data input (TDI) pin, a TAP data output (TDO) pin, a TAP mode select (TMS) pin, and a TAP clock (TCK) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register for performing boundary scan testing, a bypass register for providing a minimum path between the TDI and TDO pins, and optional design specific test data registers, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control signals at the TMS pin and clock signals at the TCK pin and to provide control and clock signals for controlling operation of the TIR and TDR's, said TAP controller comprising a n state finite machine of a plurality of flip flops, said TAP controller having a test logic reset state in which the test access port is inactive and a plurality of test mode states when the test access port is active, said registers and TAP controller of the ECL test access port comprising ECL gates with respective ECL current sinks, the improvement comprising:

• said TAP controller comprising a switch control signal (SCS) logic circuit coupled to the outputs of the flip flops of the n state finite machine of the TAP controller for generating a current sink switch control signal SCS having a first logic value when the TAP controller is in the inactive test logic reset state and a second logic value when the TAP controller is in an active test mode state;
• a current sink switch circuit coupled to respective current sinks of ECL gates incorporated in selected registers of the TAP, namely the boundary scan register, design specific TAP data registers, and TAP instruction register (TIR) said current sink switch circuit having an input coupled to receive the current sink switch control signals SCS and being constructed to turn on and off said respective current sinks of the selected registers, turning off the current sinks in response to said SCS signal first logic value to reduce power dissipation during the test logic reset (TLR) inactive state of the TAP controller, and turning on the current sinks in response to said SCS signal second logic value for operation of the TAP during active test mode states of the TAP controller.