Semiconductor integrated circuit device having a memory and an operational unit integrated therein

A semiconductor integrated circuit memory device on a single chip, comprising:

• a single array of memory cells arranged in a matrix of rows and columns, said memory cell array divided into first and second groups of memory cell columns, each group of memory cell columns comprising a plurality of bit arrays each formed of a predetermined number of columns of memory cells in adjacent positions, the predetermined number of columns of memory cells in adjacent positions comprising each of the bit arrays of said first group being interdigitated alternately with the predetermined number of columns of memory cells in adjacent positions comprising each of the bit arrays of said second group,
• first and second means corresponding respectively to said first and second groups and each responsive to an address signal for selecting one of said rows of memory cells for each group and for selecting one memory cell in each bit array in a selected row in each said group for access, each such selected cell located in the same column position in the respective bit array;
• reading means for reading data stored in selected cells;
• and
• operational means comprising a plurality of operational circuits, each corresponding to a respective bit array, for performing a predetermined operation on data provided by said reading means.

A semiconductor integrated circuit device comprising:

• a memory cell array including a plurality of memory cell groups, each of said memory cell groups including a plurality of bit arrays each having memory cells arranged in a matrix form of at least one column and a plurality of rows, the memory cells of each of said plurality of bit arrays of said plurality of memory cell groups being arranged adjacent to the memory cells of a bit array of another memory cell group;
• a plurality of selecting means provided corresponding to said plurality of memory cell groups in said memory cell array, respectively, and responsive to address signals applied independently for said groups for selecting memory cells designated by said address signals from corresponding memory cell groups;
• and
• a plurality of operation circuits each provided corresponding to respective bit arrays of the memory cell groups.

A semiconductor integrated circuit device comprising:

• a memory cell array including a plurality of memory cell groups, each of said memory cell groups including a plurality of bit arrays with each bit array having memory cells arranged in a matrix form of a plurality of rows and a plurality of columns, the memory cells of each of said plurality of bit arrays of said plurality of memory cell groups being arranged adjacent to the memory cells of a bit array of another memory cell group;
• a plurality of selecting means each provided corresponding to each bit array of each memory cell group in said memory cell array for selecting one column in each bit array, and responsive to address signals applied independently for said groups for selecting memory cells designated by said address signals from corresponding memory cell groups;
• and
• a plurality of operation circuits each provided corresponding to the bit arrays of each group having the same column position.