Method and apparatus for performing finite field division

An algebraic decoder for decoding digital symbols represented by elements of a finite field, wherein elements of the finite field are defined by a primitive polynomial, the algebraic decoder comprising:

• a dividend input which accepts a dividend element, said dividend element being an element of the finite field;
• a divisor input which accepts a divisor element, said divisor element being an element of the finite field;
• a first reference memory element;
• a second reference memory element;
• a first divisor memory element;
• a second divisor memory element;
• first initializing means for loading said divisor element into said first reference memory element;
• second initializing means for loading the primitive polynomial into said second reference memory element;
• third initializing means for loading the dividend into said first divisor memory element;
• fourth initializing means for initializing said second divisor memory element to zero;
• and
• manipulating means coupled to said first and second reference memory elements, for manipulating contents of said first and second reference memory elements according to Euclid's algorithm which has been modified such that operations of Euclid's algorithm are reduced modulo the primitive polynomial;
• and
• operation linking means, coupled to said manipulating means and said first and second divisor memory elements, for parallelling said operations of said manipulating means with said first and second divisor memory elements, thereby reducing contents of said first divisor memory element to a quotient element upon completion of said modified Euclid's algorithm.

A digital filter for dividing, over a finite field, a dividend element by a divisor element to form a quotient element, wherein the dividend element, the divisor element, and the quotient element are each elements of the finite field, wherein elements of the finite field are defined by a primitive polynomial, the digital filter comprising:

• a) a first reference register;
• b) a second reference register;
• c) a first divisor register;
• d) a second divisor register;
• e) initialization means, coupled to input ports of the digital filter, said reference registers and said divisor registers, for loading, as initial values, the divisor element into said first reference register, the primitive polynomial into said second reference register, the dividend element into said first divisor register, and zero into said second divisor register;
• f) a manipulation circuit, comprising:
• 1) a divider with inputs coupled to said first and second reference registers and outputs for a quotient and a remainder, said quotient and said remainder being results of a polynomial division of contents of said second reference register by contents of said first reference register;
• 2) a first transfer circuit coupled between said first and second reference registers, for transferring contents of said first reference register into said second reference register;
• 3) a second transfer circuit coupled between said divider and said first reference register, for transferring said remainder into said first reference register;
• g) operation linker circuit, coupled to said manipulation circuit and said first and second divisor registers, for applying to said divisor registers operations which are parallel to operations applied to said first and second reference registers by said manipulation circuit, thereby reducing the dividend element to the quotient element when said modified Euclid's algorithm reaches a final step, said operation linkage circuit comprising:
• 1) a multiplier coupled to said first divisor register and said divider, for forming a first intermediate result which is a polynomial multiplication of said first divisor register contents and said quotient;
• 2) reducing means, coupled to said multiplier, for reducing said first intermediate result modulo the primitive polynomial in the finite field to form a second intermediate result;
• 3) differential adder, coupled to said second divisor register and said reducing means, for forming a third intermediate result which is a polynomial subtraction difference of said second intermediate result and said second divisor register contents;
• 4) third transfer circuit coupled between said first divisor register to said second divisor register for transferring contents of said first divisor register to said second divisor register;
• and
• 5) fourth transfer circuit for transferring said third intermediate result from said differential adder to said first divisor register;
• and
• h) output means, coupled to said operation linkage circuit, for outputting the quotient element so calculated.

A digital filter for dividing, over a finite field, a dividend element by a divisor element to form a quotient element, wherein the dividend element, the divisor element, and the quotient element are each elements of the finite field, wherein elements of the finite field are defined by a primitive polynomial, the digital filter comprising:

• a first reference register;
• a second reference register;
• a first divisor register;
• a second divisor register;
• initialization means, coupled to input ports of the digital filter, said reference registers and said divisor registers, for loading, as initial values, the divisor element into said first reference register, the primitive polynomial into said second reference register, the dividend element into said first divisor register, and zero into said second divisor register;
• and
• manipulation means, coupled to said reference registers, for manipulating contents of said reference registers according to a modified Euclid's algorithm, wherein operations are modulo the primitive polynomial;
• operation linkage means, coupled to said manipulation means and said divisor registers, for applying to said divisor registers operations corresponding to operations applied to said reference registers by said manipulation means, reducing the dividend element to the quotient element when said modified Euclid's algorithm reaches a final step;
• and
• output means, coupled to the operation linkage means, for outputting the quotient element so calculated.

A division circuit comprising:

• an input for accepting a continuous stream of operand pairs at a clock rate, an operand pair comprising a dividend element and a divisor element;
• an input for accepting a primitive polynomial;
• an initialization input for accepting an initialization signal;
• a reference register which holds a reference value;
• reference register initialization means, coupled to said initialization input and said reference register, for initializing said reference register value to a divisor element of a current operand pair when said initialization signal is asserted;
• reference recursion logic for manipulating said reference value in response to a plurality of control signals applied at a plurality of inputs to said reference recursion logic;
• a divider register which holds a divider register value;
• divider register initialization means, coupled to said initialization input and said divider register, for initializing said divider register value to a dividend element from said current operand pair when said initialization signal is asserted;
• divider recursion logic for manipulating said divider value in response to a plurality of control signals applied at a plurality of inputs to said divider recursion logic;
• manipulation logic means, with a plurality of inputs coupled to said reference recursion logic and a plurality of control outputs, for controlling said reference recursion logic and said divider recursion logic, wherein said control outputs are coupled to said plurality of inputs to said reference recursion logic and to said plurality of inputs to said divider recursion logic, said manipulation logic means controlling said reference recursion logic to cause said reference recursion logic to manipulate said reference value into a finite field element of degree zero by evaluating said plurality of inputs, whereby said plurality of control outputs simultaneously controls said divider recursion logic to cause said divider recursion logic to manipulate said divider value from said dividend element into a quotient element for said current operand pair, wherein said quotient element is equal to a finite field division of said dividend element by said divisor element of said current operand pair modulo said primitive polynomial, where dividend elements, divisor elements, and quotient elements are each elements of a finite field;
• manipulation logic initialization means coupled to said initialization input, for resetting said manipulation logic means in response to said initialization signal being asserted;
• and
• an output for providing a continuous output stream of quotient elements at the clock rate, including said quotient element of said operand pair.