Frequency synchronized bidirectional radio system

A bidirectional radio communication system comprised of at least one communication cell, said cell having a base station and at least one remote station, said remote station receiving a polling signal at a precise base clock rate on a precise base carrier frequency from said base station, said remote station transmitting response signals at a remote clock rate to said base station on a remote carrier frequency, said remote station being comprised of:

• a first frequency synthesizer generating said remote carrier frequency, said remote carrier frequency being stabilized by a first stabilization signal directed to said first synthesizer;
• a first frequency heterodyne, said first heterodyne heterodyning said remote carrier frequency and polling signal received from said base station to generate an intermediate frequency signal;
• a second frequency synthesizer generating an intermediate frequency sinusoid, said intermediate frequency sinusoid being stabilized by a second frequency stabilization signal;
• a second frequency heterodyne, said second heterodyne heterodyning said intermediate frequency sinusoid and said intermediate frequency signal to generate a baseband signal;
• a first recovery circuit, said first recovery circuit recovering carrier frequency error information from said baseband signal and generating said first frequency stabilization signal;
• and
• a second recovery circuit, said second recovery circuit generating said second frequency stabilization signal from said baseband signal, and synchronizing said remote clock rate and said precise base clock rate.

An apparatus for decoding in-phase and quadrature components of a quadrature encoded signal, said quadrature encoded signal having a first component and a second component, said first component being an estimated in-phase component add raid second component being an estimated quadrature component, said apparatus being comprised of:

• a) a rotator, said rotator generating a first rotated component and a second rotated component from said first component and said second component in response to a rotation signal;
• b) a phase detector, said phase detector detecting an amount of in-phase component and quadrature components in said first component and said second component and generating a ramp control signal;
• c) a ramp estimator, said ramp estimator reading said ramp control signal and generating said rotation signal such that said first and second rotated components are substantially equivalent to the in-phase and quadrature components of said quadrature encoded signal;
• d) a coarse clock estimator, said coarse clock estimator generating a sequence of coarse clock pulses from said first and second rotated components;
• and
• e) a fine clock timing error estimator sampling said coarse clock pulses to produce clock timing error information from values of said first and second rotated components, said timing error information being utilized in phase-lock loop circuitry to stabilize said clock pulses.