High resolution programmable pulse generator employing controllable delay

A high resolution programmable delay circuit (HRPDC) having a delay which is at least an order of magnitude lower than the delay of a logic gate, and which provides timing-on-the-fly capabilities, comprising:

• a first logic gate having an input for receiving a signal provided by a clock having a clock cycle time and an output;
• a second logic gate having an input connected to the output of the first logic gate and an output for provided a signal which is delayed with respect to the signal provided by the clock;
• means for loading connected to the output of the first logic gate comprising at least one loading block, each of said at least one loading blocks having a loading input and a control input, wherein the loading input is connected to the output of the first logic gate, the control input provides a control signal which determines the amount of loading on said first logic gate, thereby controlling the amount of delay by which a signal outputted at the output of said second logic gate is delayed with respect with respect to the signal provided by the clock, and wherein
• said control input provides a new control signal after a time interval which is equal to the cycle time of the clock, said cycle time being greater or equal than the time required for said clock signal to propagate through said first and second logic gates.

A compounded high resolution programmable delay circuit having a clock input, a control input and an output, said compounded high resolution programmable delay circuit comprising:

• a plurality of high resolution programmable delay circuits (HRPDCs), wherein each of said HRPDCs has an output, a clock input to provide a clock signal having a cycle time, a control input providing a control signal that controls the amount of delay by which a signal is outputted at said output, wherein said outputted signal is delayed with respect to said clock signal,
• said HRPDCs are connected to each other in series by connecting the output of one of said HRPDCs to the clock input of the next HRPDC;
• and
• a plurality of delay blocks, wherein the number of said delay blocks is one less than the number of HRPDCs, each of said delay blocks having an input and an output
• said delay blocks are inserted between the control inputs of said HRPDCs by connecting the input of one of said delay blocks to the control input of one of said HRPDCs, and the output of said one of the delay blocks to the control input of the next of said HRPDCs,
• the input of the first of said delay blocks is the control input of the compounded HRPDC, thereby
• moving the control signal in step with the clock signal, and wherein
• said control input of the compounded HRPDC provides a new control signal after a time interval which is equal to the cycle time of the clock, said cycle time being less than the time required for said clock signal to propagate through said plurality of HRPDCs.

A programmable delay structure, comprising:

• N compounded HRPDCs, each of said compounded HRPDCs having a clock input, a control input and an output, wherein N being a positive integer,
• said compounded HRPDCs are connected to each other in series by connecting the output of one of said compounded HRPDC to the clock input of the next compounded HRPDC, wherein
• the first of said compounded HRPDCs includes 2.sup.0 HRPDCs, the second includes 2.sup.1 HRPDCs, and the Nth of said compounded HRPDCs includes 2.sup.N-1 HRPDCs, and wherein
• the delay through the programmable delay structure is:
• t.sub.total =t.sub.fixed +D.times.t.sub.HRPDC
• in which
• t.sub.total is the delay through the structure,
• t.sub.fixed is the minimum delay through all the HRPDCs, and
• t.sub.HRPDC is the difference between the delay through the HRPDC when the control input of said HRPDC is in a predetermined binary state and the delay through said HRPDC when the control input is in the opposite binary state, and
• D is a number that corresponds to the number of HRPDCs which are in an active state.

A programmable pulse generator for providing a linear, high resolution delay over a wide range of delays, for providing delay overlap, and for shaping an output pulse with edges of predefined shape, comprising:

• a timing control array having a plurality of inputs and outputs, each input is connected to a respective data line for selecting a predetermined delay to be generated, said array having address lines for determining an address;
• N timing generators, N being a positive number, each of said N timing generators having a clock input driven by clocking means, a plurality of control input lines connected to the outputs of said timing control array and an output to provide a signal which is delayed with respect to said clock input signal;
• and
• a data formatter having N inputs and an output, wherein
• each of said inputs is respectively driven by one of said N timing generators outputs, and wherein
• each of said inputs controls the position of a signal's rising or falling edge at said output,
• said data formatter combines signals at said N inputs into pulses having rising and falling edges that are delayed with respect to said input clock signal.

A high resolution programmable delay circuit having a delay which is at least an order of magnitude lower than the delay of a logic gate, and which provides timing-on-the-fly capabilities, comprising:

• a logic gate having an input for receiving a signal provided by a clock having a clock cycle time and one output for providing a signal which is delayed with respect to the clock signal;
• means for loading connected to the output of the logic gate comprising at least one loading block, each of said at least one loading blocks having:
• a loading input and a control input, the loading input is connected to the output of the logic gate, the control input provides a control signal which determines the amount of loading on said logic gate, thereby controlling the amount of delay by which a signal outputted at the output of said logic gate is delayed with respect of the signal provided by the clock, and wherein
• said control input provides a new control signal after a time interval which is equal to the cycle time of the clock, said cycle time being greater than or equal to the time required for said clock signal to propagate through said logic gate.