Delay matching circuit

A delay matching circuit for use with a flip-flop, the flip-flop comprising a first and a second portion, the first portion of the flip-flop coupled to the second portion of the flip-flop, the second portion propagating a logic state received from the first portion responsive to a first state of a control signal, the second portion comprising a first and a second node, a coupling circuit and a latch circuit, the first node coupled to the coupling circuit, the coupling circuit characterized by a first impedance, the coupling circuitry coupling the first portion of the flip-flop to the first node responsive to the control signal, the latch circuit storing a logic state in a first mode, the latch circuit comprising a first and a second circuit path between the first and second nodes, the first circuit path characterized by a second impedance in the first mode, the second circuit path characterized by a third impedance, and the second node characterized by a fourth impedance associated with the first circuit path, the delay matching circuit comprising:

• a third node and a fourth node;
• a first loading circuit coupled to the third node and to a second voltage supply terminal, the first loading circuit coupling the second voltage supply terminal to the third node responsive to a first predetermined state of the control signal, the first loading circuit characterized by the first impedance;
• a second loading circuit coupled to the third node and to a first voltage supply terminal, the second loading circuit coupling the first voltage supply terminal to the third node responsive to a second predetermined state of the control signal, the second loading circuit characterized by the second impedance;
• a buffer circuit electrically coupling the third and fourth nodes, the buffer circuit characterized by the third impedance;
• and
• a third loading circuit coupled to the fourth node, the third loading circuit characterized by the fourth impedance.

An apparatus for controlling a propagation delay, the apparatus comprising:

• a phase/frequency detector comprising a first and a second input, the first and second input receiving a first and a second clock signal, the first and second clock signal each characterized by a phase and a frequency, the phase/frequency detector generating a first control signal responsive to a phase difference between the first and second clock signals and a frequency difference between the first and second clock signals;
• an oscillator circuit coupled to the phase/frequency detector, the oscillator circuit generating an output clock signal characterized by a phase and a frequency, the phase and frequency of the output clock signal responsive to the first control signal;
• a frequency reducing circuit comprising an input and an output, the input receiving a selected clock signal and the output generating a reduced frequency clock signal, the selected clock signal and the reduced frequency clock signal each characterized by a frequency, a ratio of the two frequencies corresponding to a predetermined ratio, the input receiving one of either a reference clock signal or to the output clock signal of the oscillator circuit, the output generating one of either the first or second inputs of the phase/frequency detector;
• a delay matching circuit receiving the remaining one of either the reference clock signal or the output clock signal of the oscillator circuit and generating the remaining one of either the first or second inputs of the phase/frequency detector, the delay matching circuit comprising:
• a first node and a second node;
• a first loading circuit coupled to the first node and to a second voltage supply terminal, the first loading circuit coupling the second voltage supply terminal to the first node responsive to a first state of a control signal, the first loading circuit characterized by a first predetermined electrical impedance;
• a second loading circuit coupled to the first node and to a first voltage supply terminal, the second loading circuit coupling the first voltage supply terminal to the first node responsive to a second state of the control signal, the second loading circuit characterized by a second predetermined electrical impedance;
• a buffer circuit electrically coupling the first and second nodes, the buffer circuit characterized by a third predetermined electrical impedance;
• and
• a third loading circuit coupled to the second node, the third loading circuit characterized by a fourth predetermined electrical impedance.