Integrated circuit package for flexible computer system alternative architectures

A single-packaged central processing unit (CPU) formed on a substrate for a particular application in a variable word length computer system that includes a program memory storing a particular program instruction set, the substrate including means for coupling the CPU to external circuits, the CPU comprising:

• first chip means of a general purpose type comprising a plurality of elements including an arithmetic logic unit (ALU), a program counter, at least one register, and means for interconnecting the elements, said first chip means having an active surface;
• and
• second chip means having an active surface and mounted on said first chip means such that the active surface of said first chip means is facing the active surface of said second chip means, said second chip means configured for the particular application in accordance with the particular program instruction set, said second chip means comprising:
• means for receiving fetched commands from the program memory,
• means for decoding the fetched commands and for generating corresponding control signals for supplying to said first chip means, and
• means for generating system clock signals for supplying to said first chip means:
• wherein said first chip means performs operations in accordance with the control signals generated by said decoding means of said first chip means.

An integrated circuit package, comprising:

• a first pin grid array package including:
• a first ceramic layer having a plurality of connector pins,
• a second ceramic layer mounted on said first ceramic layer and having an opening,
• a third ceramic layer mounted on said second ceramic layer and having an opening larger than and over the opening of said second ceramic layer, said third ceramic layer including a plurality of sockets,
• a first semiconductor chip mounted on said first ceramic layer within the two openings,
• a plurality of connection means for coupling said first semiconductor chip to a selected number of said sockets, for coupling said first semiconductor chip to a selected number of said connector pins, and for coupling a selected number of said sockets to a selected number of said connector pins, and
• a lid mounted on said third ceramic layer and covering said first semiconductor chip;
• and
• a second package including:
• a first ceramic layer having a plurality of connector pins respectively coupled to said sockets on said third ceramic layer in said first package,
• a second ceramic layer mounted on said first ceramic layer in said second package and having an opening,
• a third ceramic layer mounted on said second ceramic layer in said second package and having an opening larger than and over the opening of said second ceramic layer in said second package,
• a second semiconductor chip mounted on said first ceramic layer in said second package within the two openings in said second package, and coupled to said connector pins on said first ceramic layer in said second package, and
• a lid mounted on said third ceramic layer and covering said second semiconductor chip:
• wherein said first and second semiconductor chips are electrically coupled together and form a central processing unit (CPU).

An integrated circuit package, comprising:

• a first package including:
• a first ceramic layer,
• a second ceramic layer mounted on said first ceramic layer and having an opening,
• a third ceramic layer mounted on said second ceramic layer and having an opening larger than and over the opening of said second ceramic layer, said third ceramic layer including a plurality of connector pins,
• a first semiconductor chip mounted on said first ceramic layer within the two openings, said first semiconductor chip being of a general purpose type and comprising a plurality of elements including an arithmetic logic unit (ALU), a program counter, at least one register, and means for interconnecting the elements.
• a plurality of connection means for coupling said first semiconductor chip to a selected number of said connector pins, for coupling said first semiconductor chip to external circuits, and for coupling a selected number of said connector pins to the external circuits, and
• a lid mounted on said third ceramic layer and covering said first semiconductor chip;
• and
• a second package including:
• a second semiconductor chip coupled to said first semiconductor chip and a selected number of said connector pins via said connection means, said second semiconductor chip being configured for a particular application in accordance with a particular program instruction set and including:
• a command register for receiving fetched commands,
• a command decoder for decoding the fetched commands and for generating corresponding control signals for supplying to said first semiconductor chip, and
• a timing generator for generating system clock signals for supplying to said first semiconductor chip;
• wherein said first semiconductor chip performs operations in accordance with the control signals generated by said command decoder of said second semiconductor chip;
• and
• said first and second semiconductor chips form a central processing unit (CPU) for the particular application in a variable word length computer system that includes a program memory storing the particular instruction set.