US 5,375,079 AGranted

Arithmetical unit including accumulating operation

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsShinichi Uramoto, Kazuya Ishihara

Life of this patent

Estimating the term…

Abstract

An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N<M) adder, a first latch having an input coupled to the output of the adder and an output coupled to an input of the adder for latching the adder output when a first clock signal is asserted, an (M-N) bit incrementer, a second latch having an input coupled to the output of the incrementer and an output coupled to the input of the incrementer for latching the incrementer output when a second clock signal is asserted, and a clock generating circuit for asserting the second clock signal in synchronism with the first clock signal only when a carry signal is generated by the adder.

Claims5

Dependent claims

An arithmetical unit for performing an accumulation operation on binary numbers including a first predetermined number of bits and forming an accumulation result being a binary number including a second predetermined number of bits, with the bits in the accumulation result grouped into said first predetermined number of low-order bits and a third predetermined number, equal to the difference between the first and second predetermined numbers, of high-order bits, said arithmetic unit comprising:

first storing means, having an input port, an output port, and a clock signal input for receiving a first clock signal, for latching the low-order bits of said accumulation result when said first clock signal is asserted,
second storing means, having an input port, an output port, and a clock signal input for receiving a second clock signal, for latching the high-order bits of said accumulation result when said second clock signal is asserted,
an adder, having first and second input ports, an output port, and a carry output that provides a carry signal, with the first input coupled to receive an input binary number having said first predetermined number of bits, a second input port coupled to the output port of said first storing means, and an output port coupled to the input port of said first storing means, said adder for adding said input signal and said low-order bits of said accumulation result to output the low-order bits of an updated accumulation result and for asserting the carry signal if a carry is generated,
an incrementer, having an input port coupled to the output port of said second storing means and an output port coupled to the input port of said second storing means for outputting an incremented value obtained by incrementing the high-order bits latched by the second storing means, and;
a logic circuit, having inputs coupled to receive said first clock signal and said carry signal, for asserting said second clock signal in synchronism with said first clock signal only when said carry signal is asserted so that the incremented value is latched by said second storing means only when said carry signal is asserted.

2 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

first storing means, having an input port, an output port, and a clock signal input for receiving a first clock signal, for latching the low-order bits of said accumulation result when said first clock signal is asserted,
second storing means, having an input port, an output port, and a clock signal input for receiving a second clock signal, for latching the high-order bits of said accumulation result when said second clock signal is asserted,
an adder, having first and second input ports, an output port, and a carry output that provides a carry signal, with the first input coupled to receive an input binary number having said first predetermined number of bits, a second input port coupled to the output port of said first storing means, and an output port coupled to the input port of said first storing means, said adder for adding said input signal and said low-order bits of said accumulation result to output the low-order bits of an updated accumulation result and for asserting the carry signal if a carry is generated,
an incrementer, having an input port coupled to the output port of said second storing means and an output port coupled to the input port of said second storing means for outputting an incremented value obtained by incrementing the high-order bits latched by the second storing means, and;
a logic circuit, having inputs coupled to receive said first clock signal and said carry signal, for asserting said second clock signal in synchronism with said first clock signal only when said carry signal is asserted so that the incremented value is latched by said second storing means only when said carry signal is asserted.

2 more elements