Balanced, high-speed differential input stage for Op-amps

A differential input circuit, comprising:

• a first half of a differential input circuit, including:
• a first differential input voltage terminal;
• a first emitter follower having a base terminal connected to the first differential input terminal, having a collector terminal connected to a first voltage terminal, and having an emitter terminal connected to a first terminal of an emitter resistor;
• a second emitter follower having a base terminal connected to the first differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal;
• a first diode-connected transistor having an emitter terminal connected to the emitter terminal of the second emitter follower and having a base terminal and a collector terminal connected together;
• a first current source having a first output terminal connected to the base and collector terminals of the first diode-connected transistor and having a second input terminal connected to a second voltage terminal;
• and
• a first output drive transistor having a base terminal connected to the base and collector terminals of the first diode-connected transistor, having an emitter terminal connected to a first terminal of an emitter resistor and to the emitter terminal of the first emitter follower, and having a collector terminal for providing a first differential output current;
• and
• a second half of a differential input circuit, including:
• a second differential input voltage terminal;
• a third emitter follower having a base terminal connected to the second differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal connected to a second terminal of the emitter resistor;
• a fourth emitter follower having a base terminal connected to the second differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal;
• a second diode-connected transistor having an emitter terminal connected to the emitter terminal of the fourth emitter follower and having a base terminal and a collector terminal connected together;
• a second current source having a first output terminal connected to the base and collector terminals of the second diode-connected transistor, and having a second terminal connected to the second voltage terminal;
• and
• a second output drive transistor having a base terminal connected to the base and collector terminals of the second diode-connected transistor, having an emitter terminal connected to the second terminal of the emitter resister and to the emitter of the third emitter follower, and having a collector terminal for providing a second differential output current.

A balanced differential input circuit, comprising:

• a first PNP transistor having a base terminal connected to a non-inverting input terminal, having a collector terminal connected to a negative voltage supply terminal, and having emitter terminal;
• a first NPN transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the first NPN transistor is connected to the emitter terminal of the first PNP transistor;
• a first current source, having an output terminal connected to the base and collector terminals of the first NPN transistor and having an input terminal connected to a positive voltage supply terminal;
• a second PNP transistor having a base terminal connected to the non-inverting input terminal, having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal;
• a second NPN transistor having its base terminal coupled to the base terminal of the second PNP transistor, having an emitter terminal coupled to the emitter terminal of the second PNP transistor and coupled to one terminal of an emitter impedance, and having a collector terminal connected to a first differential output terminal;
• a third PNP transistor having a base terminal connected to an inverting input terminal having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal;
• a third NPN transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the third NPN transistor is connected to the emitter terminal of the third PNP transistor;
• a second current source, having an output terminal connected to the base and collector terminals of the third NPN transistor and having an input terminal connected to the positive voltage supply terminal;
• a fourth PNP transistor having a base terminal connected to the inverting input terminal for the operational amplifier, having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal;
• a fourth NPN transistor having its base terminal coupled to the base terminal of the third NPN transistor, having an emitter terminal coupled to the emitter terminal of the fourth PNP transistor and coupled to another terminal of the emitter impedance, and having a collector terminal connected to a second differential output terminal.

A balanced differential input circuit, comprising:

• a first NPN transistor having a base terminal connected to a non-inverting input terminal, having a collector terminal connected to a positive voltage supply terminal, and having an emitter terminal;
• a first PNP transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the first PNP transistor is connected to the emitter terminal of the first NPN transistor;
• a first current source, having an input terminal connected to the base and collector terminals of the first PNP transistor and having an output terminal connected to a negative voltage supply terminal;
• a second NPN transistor having a base terminal connected to the non-inverting input terminal, having a collector terminal connected to the positive voltage supply terminal, and having an emitter terminal;
• a second PNP transistor having its base terminal coupled to the base terminal of the first PNP transistor, having an emitter terminal coupled to the emitter terminal of the second NPN transistor and coupled to one terminal of an emitter impedance, and having a collector terminal connected to a first differential output terminal;
• a third NPN transistor having a base terminal connected to an inverting input terminal, having a collector terminal connected to a positive voltage supply terminal, and having an emitter terminal;
• a third PNP transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the third PNP transistor is connected to the emitter terminal of the third NPN transistor;
• a second current source, having an input terminal connected to the base and collector terminals of the third PNP transistor and having an output terminal connected to the negative voltage supply terminal;
• a fourth NPN transistor having a base terminal connected to the inverting input terminal, having a collector terminal connected to the positive voltage supply terminal, and having an emitter terminal;
• a fourth PNP transistor having its base terminal coupled to the base terminal of the third PNP transistor having an emitter terminal coupled to the emitter terminal of the fourth NPN transistor and coupled to another terminal of the emitter impedance, and having a collector terminal connected to a second differential output terminal.