Data processor a method and apparatus for performing postnormalization in a floating-point execution unit

In a data processor having a register file for storing a plurality of floating-point data operands, each of said floating-point data operands having a mantissa portion, an exponent portion and a sign bit, and an execution unit for executing a plurality of floating-point operations using a selected number of said plurality of floating-point data operands, a method for performing postnormalization during a floating-point addition/subtraction operation to determine a final floating-point result, said method comprising the steps of:

• adding, via a mantissa adder, said mantissa portion of a first data operand to said mantissa portion of a second data operand to generate a prenormalized mantissa sum comprising a mantissa value and a carry bit, while simultaneously incrementing, via an exponent incrementer said exponent portion of a larger one of said first data operand and said second data operand by two to generate an incremented exponent;
• normalizing, via a first logic portion, the prenormalized mantissa sum, to generate a post normalized mantissa sum, said first logic portion determining a number of leading zero bits in said prenormalized mantissa sum and providing an encoded value as an output signal representing said number of leading zero bits;
• rounding, via a rounding logic portion, said postnormalized mantissa sum and providing a rounded mantissa value and a overflow output signal, while simultaneously adjusting, via an exponent adjust adder said incremented exponent to generate a first exponent result value and a second exponent result value;
• performing, via a shifter, a one bit right-shift of said rounded mantissa value to generate a right shifted mantissa value when an overflow condition occurred as a result of performing said rounding of said postnormalized mantissa sum;
• selecting, via a select logic portion, based upon a value of said overflow output signal, either said first exponent result or said second exponent result as a final exponent result;
• and
• providing, via a writeback logic portion said final exponent result, said rounded mantissa value and a result sign bit in said register file as said final floating-point result.

A data processor having a register file, for storing a plurality of floating-point data operands, where each of said floating-point data operand has a mantissa portion, an exponent portion, and a sign bit, and a floating-point execution unit for performing a floating-point addition/subtraction operation to determine a floating-point result, said execution unit comprising:

• mantissa logic circuitry for adding said mantissa portion of a first data operand to said mantissa portion of a second data operand to generate a prenormalized mantissa sum comprising a mantissa value and a carry bit, and for normalizing the prenormalized mantissa sum, to generate a post normalized mantissa sum, said mantissa logic circuitry determining an encoded value representing a number of leading zero bits in said prenormalized mantissa sum and generating a first output signal representing said encoded value, said mantissa logic circuitry left-shifting said prenormalized mantissa sum by said encoded value to generate said post normalized mantissa sum, and rounding said postnormalized mantissa sum to provide a rounded mantissa value as a mantissa result, and said mantissa logic circuitry examining a carry output signal generated during rounding of said postnormalized mantissa value to determine whether an overflow condition occurred and providing an overflow output signal indicative thereof,
• exponent logic circuitry coupled to said mantissa logic circuitry for incrementing said exponent portion of a larger one of said first data operand and said second data operand by two to generate an incremented exponent, and for subtracting said encoded value from said incremented exponent to generate a first exponent result value, and adjusting said incremented exponent to generate a second exponent result value, in response to receiving said first output signal from said mantissa logic circuitry, said exponent logic circuitry receiving said overflow output signal from said mantissa logic circuitry and selecting either said first exponent result or said second exponent result as a final exponent result, in response thereto;
• and
• writeback control logic circuitry coupled to said mantissa logic circuitry and said exponent logic circuitry for providing said final exponent result, said mantissa result and a result sign bit to said register file as said final floating-point result.