Clamping circuit with offset compensation for analog-to-digital converters

A voltage clamping circuit for clamping the output signal of an analog-to-digital converter to a reference value comprising:

• an input for receiving an input signal;
• a clamp capacitor coupled to said input;
• an analog charge loop coupled to said clamp capacitor, said analog charge loop including a differential amplifier having an output for supplying an output current for charging said clamp capacitor, said differential amplifier having inverting and non-inverting inputs, said output current having a first offset value offset from a difference value of signals applied to said inverting and non-inverting inputs, said inverting input receiving an analog voltage corresponding to the charge on said clamp capacitor;
• an analog-to-digital (A/D) converter for digitizing said analog voltage into a digital output signal, said A/D converter digital output signal tending to be offset from said reference value by a second offset value;
• and
• means responsive to said digital output signal for generating a correction signal and for applying the correction signal to said non-inverting input of said differential amplifier to correct for said first and second offset values such that said digital output signal is substantially at said reference value.

A voltage clamping circuit for clamping the output signal of an analog-to-digital (A/D) converter to a reference value comprising:

• an input for receiving an input signal;
• a clamp capacitor coupled to said input;
• an analog charge loop coupled to said clamp capacitor, said analog charge loop including amplifier means having an output for supplying an output current for charging said clamp capacitor in accordance with relative values of first and second input signals applied to respective first and second input terminals of said amplifier means, said output current having a first offset value offset from the relative value of said first and second input signals, the first input signal comprising an analog voltage corresponding to the charge on said clamp capacitor;
• an analog-to-digital (A/D) converter for digitizing said analog voltage into a digital output signal, said A/D converter digital output signal tending to be offset from said reference value by a second offset value;
• and
• correction means responsive to said digital output signal for generating a correction signal and for applying the correction signal as said second input signal to said second input terminal of said amplifier means to compensate for said first and second offsets values such that said digital output signal is substantially at said reference value.

A clamping circuit for clamping a received signal to a given reference level, comprising:

• means responsive to said received signal for generating a clamped digital output signal, including charge storage means to which said received signal is applied, and analog-to-digital converter means coupled to said charge storage means for generating said clamped digital output signal, said clamped digital output signal tending to be offset from said given reference level by an offset error in at least said analog-to-digital converter means;
• error voltage generating means for generating an error correction voltage;
• and
• means responsive to the correction voltage for correcting said clamped digital output signal to substantially correspond to said given reference level, wherein said error voltage generating means comprises comparator means responsive to said digital output signal and a digital reference signal representing said given reference level to provide a digital error signal corresponding to said error correction voltage, and said correcting means includes means responsive to said digital error signal for correcting the value of said clamped digital output signal, wherein said digital error signal comprises a binary signal having first and second values, one of said values corresponding to an error between said clamped digital output signal and said given reference level in a first direction relative to said given reference level, and the other of said values corresponding to an error in a second direction opposite the first direction, said error voltage generating means including means responsive to each of said binary signal values for generating a charge current having a given magnitude, said charge current having a first polarity corresponding to one of said binary signal values and a second opposite polarity corresponding to the other of said binary values, and further including charge means responsive to said charge currents for generating said error correction voltage.