Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks in which data is carried by data packets of variable lengths, with each data packet including a header control information portion required by communication protocols used to mediate the information exchange, and a data portion for the data which is to be communicated, comprising:

• a. a processor subsystem including a processor for processing the header control information portions of data packets, with the processor having access to data packets stored in a packet memory means;
• b. said packet memory means is organized as a three level hierarchy comprising a first level of queue sets, each of which is comprised of a second level of linked lists of data packets, with each data packet being comprised of a third level list of buffers, said packet memory means storing data packets arriving at at least one generic adapter input/output port, with each data packet being stored in one or more of said buffers as required by the length of the data packet, with an order of use of the buffers being interchangeable;
• c. a generic adapter manager means for performing and synchronizing generic adapter management functions, including implementing data structures in said packet memory means by organizing data packets in said buffers, and organizing data packets into queues for processing by said processor subsystem or transfer to or from said at least one generic adapter input/output port and processing multiple interleaved receive data streams and multiple interleaved transmit data streams;
• and
• d. said at least one generic adapter input/output port having associated therewith a packet memory interface providing for transfer of data packets into and out of said packet memory means, such that when a data packet is received at one said generic adapter input/output port, the data packet is transferred into said packet memory means and queued for processing.