Back to results
US 5,365,476 AGranted
Three-port Josephson memory cell for superconducting digital computer
AssigneeDigital Equipment Corporation
InventorOleg A. Mukhanov
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeDigital Equipment Corporation
InventorOleg A. Mukhanov
Estimating the term…
A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line. To provide non-destructive readout and wide margins, the memory cell includes a write gate responsive to the write enable pulse for storing current from the data line, a first read gate responsive to the stored current and the first read enable pulse, a second read gate responsive to the stored current and the second read enable pulse, a first buffer gate responsive to the first read gate for asserting a data output signal on the first sense line, and a second buffer gate responsive to the second read gate for asserting a data output signal on the second sense line. In the preferred construction, the current is stored in two storage loops. One storage loop includes a control current path for the first read gate, and the other storage loop includes the control current path for the second read gate.
A method of storing data in a superconducting memory cell and retrieving the stored data, said memory call receiving a data input signal from a data line, a write enable signal from a write line, a first read enable signal from a first read line, and a second read enable signal from a second read line, said memory cell transmitting a first data output signal to a first sense line and a second data output signal to a second sense line, said method comprising the steps of:
A superconducting memory cell, said memory cell receiving a data input signal from a data line, a write enable signal from a write line, a first read enable signal from a first read line, and a second read enable signal from a second read line, said memory cell transmitting a first data output signal to a first sense line and a second data output signal to a second sense line, said superconducting memory cell comprising a plurality of Josephson gates, said Josephson gates including:
A superconducting memory cell, said memory cell receiving a data input signal from a data line, a write enable signal from a write line, a first read enable signal from a first read line, and a second read enable signal from a second read line, said memory cell transmitting a first data output signal to a first sense line and a second data output signal to a second sense line, said superconducting memory cell comprising a plurality of Josephson gates, said Josephson gates including:
Dependencies are inferred from the claim text.