Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor

A method of high-speed computing comprising the steps of:

• providing a plurality of dynamically configurable gate arrays each having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and programming means for programming said I/O blocks, said logic blocks and said routing resources, said programming means defining an appropriate mode of operation for said gate array;
• providing microprocessor means coupled to an external source and implemented within each of said gate arrays by programming said programming means for processing instructions received from said external source;
• implementing reconfigurable instruction execution means within each of said gate arrays by programming said programming means, said reconfigurable instruction execution means being coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks of said gate arrays according to said information received;
• reconfiguring said reconfigurable instruction execution means by programming said programming means to change said reconfigurable execution means so an operation on data within said reconfigurable execution means is carried out by circuits within said gate arrays after said reconfiguring is complete;
• and
• programming a first of said plurality of dynamically configurable gate arrays to perform computations while said external source dynamically reconfigures a second of said plurality of dynamically configurable gate arrays.