US 5,361,337 AGranted

Method and apparatus for rapidly switching processes in a computer system

AssigneeSun Microsystems, Inc.

InventorKenneth Okin

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Abstract

An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.

Claims13

Dependent claims

In a computer system comprising a pipelined processor coupled to a memory subsystem having a cache memory and a main memory, a method for executing a plurality of processes, said method comprising the steps of:

executing a first process by a plurality of stateless elements of said pipelined processor, execution results and state information of said first process being stored by said stainless elements into a first plurality of state elements of said pipelined processor coupled to said stateless elements, said first process being an instance of a first program stored in said memory subsystem;
suspending execution of said first process by said stateless elements when encountering a first cache miss while executing said first process;
and
switching to execute a second process by said stateless elements upon suspending execution of said first process, execution results and state information of said second process being stored by said stateless elements into a second plurality of state elements of said pipelined processor coupled to said stateless elements, said second process being an instance of a second program Stored in said memory subsystem, said suspension and switching being accomplished in a first time period that is shorter than a second time period required on average by said memory subsystem to handle a cache miss. PG,17

1 more element

In a computer system comprising a memory subsystem having a cache memory and a main memory coupled to each other, an apparatus for executing a plurality of processes, said apparatus comprising:

a first plurality of state elements coupled to said memory subsystem for storing execution results and state information of a first process, said first process being an instance of a first program stored in said memory subsystem;
a second plurality of state elements coupled to said memory subsystem for storing execution results and state information of a second process, said second process being an instance of a second program stored in said memory subsystem;
and
a plurality of stateless elements coupled to said memory subsystem and said first and second plurality of state elements for executing said first process, suspending execution of said first process when encountering a first cache miss while executing said first process, and switching to execute said second process upon suspending execution of said first process, said stateless elements storing execution results and state information of said first and second processes in said first and second plurality of state elements respectively, said stateless elements accomplishing said suspension and switching in a first time period that is shorter than a second time period required on average by said memory subsystem to handle a cache miss.

1 more element

A computer system comprising:

a pipelined processor comprising a plurality of stateless elements, and a first and second plurality of state elements coupled to said stateless elements for executing one of a first and a second process, said stateless elements first executing said first process, then suspending execution of said first process when encountering a first cache miss while executing said first process, and switching to execute said second process upon suspending execution of said first process, said stateless elements storing execution results and state information of said first and second processes in said first and second plurality of state elements respectively;
and
a memory subsystem coupled to said pipelined processor having a cache memory and a main memory for storing a first and a second program, said first and second processes being instances of said first and second programs respectively, said stateless elements accomplishing said suspension anal switching in a first time period that is shorter than a second time period required on average by said memory subsystem to handle a cache miss.

Dependencies are inferred from the claim text.

Facts

Application: 07/883,059Filed 8 May 1992 · continuation
Priority: 3 Aug 1989
Granted: 1 Nov 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 9/38
Arrangements for executing machine instructions, e.g. instruction decode: concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/3867
Concurrent instruction execution, e.g. pipeline or look ahead: using instruction pipelines
G06F
Computing and data processing