US 5,359,694 A · Method and apparatus for converting image data

Abstract

A method and apparatus for converting input image data in line-scan format into block-scan format, and for converting input image data in block-scan format into line-scan format. The apparatus can be implemented as a single integrated circuit which includes a memory and control logic for implementing format conversion, but no external address lines. The apparatus includes an address generator which automatically generates an address sequence for each strip of input data. Each input data strip comprises N lines of image data words, with L vectors in each line, where each vector comprises M image data words. The apparatus converts a line-scan format input data strip into blocks each consisting of N vectors. Each input data strip is processed efficiently, by automatically generating a sequence of addresses for the vectors of the strip. During each iteration of a format conversion operation, one address is generated, one vector is read out of a memory location identified by that address, and one input vector is written into the memory location. The address generator preferably generates addresses for B input data strips which comprise an image by performing a sequence of iterations during each of B cycles, where each iteration includes the step of "modulo k" addition by an increment F, where F has a different value during each cycle. The increment F for each of the cycles following the first cycle is stored as it becomes available during performance of a previous one of the cycles.

Claims28

Dependent claims

An apparatus for converting strips of input image data in a first one of a line-scan format and a block-scan format, into output data having a second one of the line-scan format and the block-scan format, wherein B of the strips determine an input image, wherein each of the strips comprises N lines of image data words, and wherein each of the lines of image data words comprises L vectors, where B, N, and L are integers, said apparatus including:.

a random access memory, having memory locations for a strip comprising a set of vectors of the input image data, each of said vectors comprising M words of the input image data, where M is an integer;
and
an address generator, wherein the random access memory and the address generator are implemented in a single integrated circuit, and wherein the address generator includes a means for generating a sequence of address signals for the vectors of a strip of the input image data during each cycle of a cyclical address generation operation, wherein said each cycle comprises a sequence of iterations, and wherein the address generator generates an address signal for a vector of the strip during each of the iterations, wherein the address generator includes means for generating a different sequence of address signals for each of at least two strips of the input image data, during different cycles of the cyclical address generation operation, and wherein the address generator includes a means for performing B cycles of the cyclical address generation operation to generate B sequences of address signals, with each of said iterations consisting of modulo k addition by an increment F, where k=NL-1, wherein the increment F has a different value during each of said B cycles, wherein the increment F for a first one of the B cycles is a default value, and the increment F for the Yth one of the B cycles, where Y is an integer greater than one is stored as said increment F is generated during performance of the (Y-1)th one of the B cycles.

a random access memory, having memory locations for a strip comprising vectors of the input image data, each of said vectors comprising M words of the input image data, where M is an integer;
and
an address generator connected to the random access memory, and including means for performing B cycles of an address generation operation to generate B sequences of address signals for vectors of each of B strips of the input image data, where B is an integer greater than one, wherein each of the cycles includes a sequence of iterations, and
wherein the address generator generates one of said address signals for one of the vectors during each of the iterations, wherein each of said strips comprises N lines of image data words, each of said lines of image data words comprises L vectors, where N and L are integers, and wherein each of the iterations includes an operation of modulo k addition by an increment F, where k=NL-1 wherein the increment F for one of the B cycles, where Y is an integer greater than one, is stored as said increment F is generated during performance of the one of the B Cycles.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for converting image data

Life of this patent

Method and apparatus for converting image data

Life of this patent

Abstract

Claims28