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AssigneeCirrus Logic, Inc.
InventorsRichard T. Behrens, Trent Dudley, Neal Glover, David R. Welland
Estimating the term…
A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.
A phase detector for creating a phase error measurement signal representative of a difference in phase between a clock signal and pulses within an analog signal, said phase detector comprising:
A phase locked loop for creating a clock signal in phase with pulses within an analog signal, said phase locked loop comprising:
A frequency detector for creating a frequency error measurement signal representative of a difference in frequency between a periodic analog signal waveform and a clock signal, said frequency detector comprising:
A frequency locked loop for locking the frequency of a clock signal to a predetermined multiple of the frequency of a periodic input waveform signal, said frequency locked loop comprising:
A timing recovery circuit for determining a clock signal from a data signal from a data storage device or a data signal from a data communications device, said timing recovery circuit comprising:
Dependencies are inferred from the claim text.