US 5,357,473 A · Semiconductor storage system including defective bit replacement · patentgrep

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Abstract

A semiconductor storage system comprises a semiconductor storage element array including a plurality of semiconductor memory elements, a data bus for transferring data to said semiconductor storage element array, an address bus for inputting an address to said semiconductor storage element array, a read/write controller for controlling read/write of the data written to said semiconductor storage element array, an interface control module for controlling a transfer/receipt of data and commands to and from an outside system, a microprocessor for controlling said read/write controller and said interface control module, a defect address memory for storing and outputting information on an address where at least one defective bit exists and an alternate address to be substituted for said address, and a defect address manipulating circuit for substituting said alternate address for said address where said defective bit exists in accordance with an output of said defect address memory.

Claims30

Dependent claims

A semiconductor storage system comprising:

(a) a semiconductor storage element array including a plurality of semiconductor memory elements having a possibility of containing defective bits, for storing information;
(b) a data bus, having a plurality of bits, for transferring data to said semiconductor storage element array;
(c) an address bus, having a plurality of bits, for providing an address to said semiconductor storage element array;
(d) a read/write controller for controlling reading of data from and writing of data to said semiconductor storage element array;
(e) an interface control module for controlling transfer of data and commands to and receipt of data and commands from an outside system;
(f) a microprocessor for controlling said read/write controller and said interface control module;
(g) a defect address memory for storing defective addresses of said semiconductor storage element array where said defective bits have been detected and substitute addresses to be correspondingly substituted for said defective address;
and
(h) a defect address manipulating circuit for providing said corresponding substitute address from said defective address memory to said semiconductor storage element array when said defective address is accessed through said address bus.

6 more elements

A semiconductor storage system comprising:

a semiconductor storage element array including a plurality of semiconductor memory elements, said plurality of semiconductor memory elements containing one or more defective bits, said array for storing information at addresses, each of which includes a plurality of bits;
a data bus, having a plurality of bits, for transferring data to and from said semiconductor storage element array;
a DRAM controller for controlling read of data from said semiconductor storage element array and write of data to said semiconductor storage element array;
a DMA controller for controlling a data transfer by giving a start command to said DRAM controller and by giving an address for one of a reading and a writing operation to said semiconductor storage element array;
an address bus, having a plurality of bits, for transferring said address to said semiconductor storage element array from said DMA controller;
an interface control module for controlling communication of the data and commands with a host computer through a magnetic disk interface;
an ECC circuit including means for reading the data transferred from said semiconductor storage element array, means for detecting an error of data, means for correcting said error and means for inputting the data to said data bus, and further including means for generating ECC data (Error Checking and Correction code data) from the data transferred from said host computer and means for transferring data including ECC data to said semiconductor storage element array from said data bus;
a microprocessor for controlling said DMA controller and said interface control module;
a defect address memory for storing defective addresses of said semiconductor storage element array where said defective bits have been detected and substitute addresses to be correspondingly substituted for said defective address;
and
a defect address manipulating circuit for providing said corresponding substitute address from said defective address memory to said semiconductor storage element array when said defective address is accessed through said address bus.

8 more elements

A semiconductor storage system comprising:

a semiconductor storage element array including a plurality of semiconductor memory elements, said plurality of semiconductor memory elements containing one or more defective bits, said array for storing information at addresses, each of which includes a plurality of bits;
a data bus, having a plurality of bits, for transferring data to and from said semiconductor storage element array;
a DRAM controller for controlling read of data from said semiconductor storage element array and write of data to said semiconductor storage element array;
a DMA controller for controlling a data transfer by giving a start command to said DRAM controller and by giving an address for one of a reading and a writing operation to said semiconductor storage element array;
an address bus, having a plurality of bits, for transferring said address to said semiconductor storage element array from said DMA controller;
an interface control module for controlling communication of the data and commands with a host computer through a magnetic disk interface;
an ECC circuit including means for reading the data transferred from said semiconductor storage element array, means for detecting an error of data, means for correcting said error and means for inputting the data to said data bus, and further including means for generating ECC data (Error Checking and Correction code data) from the data transferred from said host computer and means for transferring data including ECC data to said semiconductor storage element array from said data bus;
a microprocessor for controlling said DMA controller and said interface control module;
a defective bit memory for storing positional information of said defective bit existing in the data to be output at said address where said defective bit exists;
a defect alternate semiconductor storage element for alternating with said defective bit;
and
a defective data manipulating circuit for replacing reads and writes of said defective bit with reads and writes of said defect alternate semiconductor storage element in accordance with said positional information in said defective bit memory.

9 more elements

A semiconductor storage system comprising:

a semiconductor storage element array including a plurality of semiconductor memory elements, said plurality of semiconductor memory elements containing one or more defective bits, said array for storing information at addresses, each of which includes a plurality of bits;
a data bus, having a plurality of bits, for transferring data to and from said semiconductor storage element array;
a DRAM controller for controlling read of data from said semiconductor storage element array and write of data to said semiconductor storage element array;
a DMA controller for controlling a data transfer by giving a start command to said DRAM controller and by giving an address for one of a reading and a writing operation to said semiconductor storage element array;
an address bus, having a plurality of bits, for transferring said address to said semiconductor storage element array from said DMA controller;
an interface control module for controlling communication of the data and commands with a host computer through a magnetic disk interface;
an ECC circuit including means for reading the data transferred from said semiconductor storage element array, detecting an error of data, means for correcting said error and means for inputting the data to said data bus, and further including means for generating ECC data (Error Checking and Correction code data) from the data transferred from said host computer and means for transferring data to said semiconductor storage element array;
a microprocessor for controlling said DMA controller and said interface control module;
a defective bit memory for storing positional information of said defective bit existing in the data to be output at said address where said defective bit exists;
a defect alternate semiconductor storage element for alternation with said defective bit;
and
a defective data manipulating circuit for replacing an output from said defective bit with an output from said defect alternate semiconductor storage element, in accordance with the positional information in said defective bit memory.

9 more elements

A computer system including a central processing unit and a semiconductor storage system, the semiconductor storage system comprising:

a semiconductor storage element array including a plurality of semiconductor memory elements, said plurality of semiconductor memory elements containing one or more defective bits, said array for storing information at addresses, each of which includes a plurality of bits;
a data bus, having a plurality of bits, for transferring data to and from said semiconductor storage element array;
a DRAM controller for controlling read of data from said semiconductor storage element array and write of data to said semiconductor storage element array;
a DMA controller for controlling a data transfer by giving a start command to said DRAM controller and by giving an address for one of a reading and a writing operation to said semiconductor storage element array;
an address bus, having a plurality of bits, for transferring said address to said semiconductor storage element array from said DMA controller;
an interface control module for controlling communication of the data and commands with a host computer through a magnetic disk interface;
an ECC circuit including means for reading the data transferred from said semiconductor storage element array, means for detecting an error of data, means for correcting said error and means for inputting the data to said data bus, and further including means for generating ECC data (Error Checking and Correction code data) from the data transferred from said host computer and means for transferring data including ECC data to said semiconductor storage element array from said data bus;
a microprocessor for general purpose control of said DMA controller and said interface control module;
a defect address memory for storing information regarding an address where at least one defective bit exists and information regarding a substitute address to be substituted for said address, and including means for providing as an output said stored information;
and
a defect address manipulating circuit for substituting said substitute address with said address where said defective bit exists in accordance with an output of said defect address memory.

8 more elements

A semiconductor storage system comprising:

a semiconductor storage element array including a plurality of semiconductor memory elements having a possibility of containing at least one defective bit, for storing information;
a data bus, having a plurality of bits, for transferring data to and from said semiconductor storage element array;
an address bus, having a plurality of bits, for providing an address to said semiconductor storage element array;
a read/write controller for controlling reading of data from and writing of data to said semiconductor storage element array;
an interface control module for controlling transfer of data and commands to and receipt of data and commands from an outside system;
a microprocessor for controlling said read/write controller and said interface module;
a defective address memory for storing defective address of said semiconductor storage element array where said defective bit has been detected and information regarding a substitute address to be correspondingly substituted for said defective address;
and
a defective address manipulating circuit interposed in said address bus, for providing the corresponding substitute address from said defective address memory to said semiconductor storage element array when said defect address is accessed through said address bus.

6 more elements

Dependencies are inferred from the claim text.