Method for reverse programming of a flash EEPROM

A method of erasing, selectively programming, and verifying a flash electrically erasable read-only memory (EEPROM) cell within an array of flash EEPROM cells arranged in rows and columns, each cell in a row having a control gate connecting a wordline and each cell in a column having a drain connection to a bitline;

• the method comprising:
• a. erasing the cell array by simultaneous application of a high positive voltage on the wordlines and having a float or zero volts on the bit lines and a grounded source, thereby providing a high threshold voltage V.sub.t on all cells;
• b. programming a selected cell or cells by application of a negative voltage on a selected wordline and application of a zero or a positive voltage on a selected bitline, thereby providing a lower threshold voltage V.sub.t on selected cells;
• c. verifying a proper data input and lower voltage V.sub.t on selected cells by application of a lower positive voltage on the selected wordline and application of a low, positive voltage on the selected bitline and floating unselected bitlines;
• and
• d. repeating the programming and verifying steps above until all cell threshold voltages V.sub.t lie within a preferred tight, normal, distribution curve.

A method of erasing, selectively programming, and verifying a flash electrically erasable read-only memory (EEPROM) cell within an array of flash EEPROM cells arranged in rows and columns, each cell in a row having a control gate connecting a wordline and each cell in a column having a drain connection to a bitline;

• the method comprising:
• a. erasing the cell array by simultaneous application of about +17 volts on the wordlines and having a float or zero volts on the bit lines, thereby providing a high threshold voltage V.sub.t on all cells;
• b. programming a selected cell or cells by application of -10 volts on a selected wordline and application of a zero or a positive voltage on a selected bitline and a grounded source, thereby providing a lower threshold voltage V.sub.t on selected cells;
• c. verifying a proper data input and lower voltage V.sub.t on selected cells by application of about +5 volts on the selected wordline and application of +1.5 volts on the selected bitline and floating unselected bitlines;
• and
• d. repeating the programming and verifying steps above until all cell threshold voltages V.sub.t lie within a preferred tight, normal, distribution curve above zero volts and below +5 volts.