Pin driver amplifier

In a pin driver adapted for transmitting driver pulses of predetermined voltage levels and timing to a device under test, an output amplifier comprising:

• a complementary pair of transistors;
• a pair of resistors coupled in series between corresponding terminals of said complementary pair of transistors;
• an output terminal adapted for connecting a transmission line leading to said device under test;
• an output resistor coupled between said output terminal and a node between said pair of series resistors;
• and
• means for maintaining a substantially constant reverse termination impedance for said transmission line notwithstanding changes in output impedance at said node, said maintaining means comprising a capacitor and resistor connected in series from said output terminal to ground.

In a pin driver adapted for transmitting driver pulses of predetermined voltage levels and timing to a device under test, an output amplifier comprising:

• a complementary pair of transistors;
• a pair of resistors connected in series between corresponding terminals of said complementary pair of transistors;
• an output terminal adapted for connecting a transmission line leading to said device under test;
• a resistor coupled between said output terminal and a node between said pair of series resistors;
• and
• a capacitor coupled between said corresponding terminals of said complementary pair of transistors.

A pin driver adapted for transmitting driver pulses of predetermined voltage levels and timing to a device under test, said pin driver comprising:

• pulse forming means responsive to a data input signal for providing a pulsed output of said predetermined voltage levels and timing in accordance with said data input signal;
• a buffer circuit comprising a pair of buffer transistors each having a base responsive to said pulsed output of said pulse forming means, said buffer circuit further comprising a pair of current sources each coupled to a respective one of corresponding terminals of said buffer transistors;
• a capacitor coupled between said corresponding terminals of said buffer transistors;
• an amplifier circuit comprising a complementary pair of transistors each having a base responsive to a respective one of said corresponding terminals of said buffer transistors;
• a pair of resistors connected in series between corresponding terminals of said amplifier transistors;
• an output terminal adapted for connecting a transmission line to transmit said driver pulses to said device under test;
• and
• an output resistor coupled between said output terminal and a node between said pair of series resistors.