Macrocell with product-term cascade and improved flip flop utilization
AssigneeXilinx, Inc.
InventorsDavid Chiang, Napoleon W. Lee, Thomas Y. Ho, David A. Harrison, Nicholas Kucharewski, Jr., Jeffrey H. Seltzer
Life of this patent
Estimating the term…
Abstract
A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.
Claims11
A programmable logic circuit comprising:
- a plurality of input lines;
- a dedicated line;
- a flip flop having a flip flop data input terminal and a flip flop output terminal;
- a first logic gate receiving input signals from said plurality of input lines, said first logic gate having a first logic gate output terminal;
- and
- a cascade circuit having first and second programmable states, said cascade circuit connecting said first logic gate output terminal to said flip flop data input terminal when in said first programmable state, said cascade circuit connecting said first logic gate output terminal to an input terminal of a second logic gate and connecting said dedicated line to said flip flop data input terminal when in said second programmable state.
A programmable logic circuit comprising:
- a plurality of input lines;
- a dedicated line;
- a first logic gate receiving input signals from said plurality of input lines, said first logic gate having a first logic gate output terminal;
- a flip flop having a flip flop data input terminal, a clock input terminal and a flip flop output terminal;
- a first multiplexer having a control terminal and two input terminals, the first input terminal connected to said first logic gate output terminal, the second input terminal connected to a reference level, said first multiplexer having an output terminal connected to an input terminal of a second logic gate;
- a second multiplexer having a control terminal and two input terminals, the first input terminal connected to said first logic gate output terminal, the second input terminal connected to said dedicated line, said second multiplexer having an output terminal connected to said flip flop data input terminal;
- a cascade control circuit connected to the control terminals of said first and second multiplexers, said cascade control circuit having first and second programmable states,
- said first programmable state:
- causing said first multiplexer to select said reference level, and
- causing said second multiplexer to select said first logic output line;
- said second programmable state:
- causing said first multiplexer to select said first logic gate output line, and
- causing said second multiplexer to select said dedicated line.
A structure for a programmable logic circuit comprising:
- a plurality of macrocells each having:
- product term input signals;
- a logic gate which receives at least said product term input signals and generates an output signal therefrom;
- a flip flop having an input terminal;
- and
- a multiplexer having a first state and a second state, wherein said first state directs said output signal to said flip flop input terminal and said second state directs another signal to said flip flop input terminal and directs said output signal to a logic gate of another macrocell as an input signal thereof;
- and in which said another signal directed to said flip flop input terminal comprises a product term output signal from an AND array.
Dependencies are inferred from the claim text.