Integrated waveshaping circuit using weighted current summing

A method for waveshaping an output data signal and a complementary output data signal, the method comprising the steps of:

• generating a plurality of incrementally-delayed timing signals in response to an externally provided oscillator signal;
• generating a plurality of pairs of logic signals in response to the plurality of incrementally-delayed timing signals, each timing signal generating one corresponding pair of logic signals by periodically latching an input data signal so that a logic state and an inverse logic state of the input data signal are simultaneously provided by the corresponding pair of logic signals;
• generating a plurality of pairs of delayed logic signals in response to the plurality of incrementally-delayed timing signals, each timing signal generating one corresponding pair of delayed logic signals by periodically latching a delayed input data signal so that a logic state and an inverse logic state of the delayed input data signal are simultaneously provided by the corresponding pair of logic signals, each pair of delayed logic signals corresponding to one pair of logic signals;
• and
• generating both the output data signal and the complementary output data signal in response to both the plurality of pairs of logic signals and the plurality of pairs of delayed logic signals, each pair of logic signals and its corresponding pair of delayed logic signals simultaneously generating both an incremental portion of the output data signal and an incremental portion of the complementary output data signal so that an instantaneous value of the output data signal is determined by summing together the incremental portions of the output data signal while an instantaneous value of the complementary output data signal is also determined by summing together the incremental portions of the complementary output data signal.

A waveshaping circuit for generating complementary output data signals, the waveshaping circuit comprising:

• an input stage that generates a plurality of pairs of logic signals within each period of a data signal in response to the data signal and a plurality of timing signals, the data signal and the timing signals having a phase relationship;
• a delayed input stage that generates a plurality of pairs of delayed logic signals within each period of a delayed data signal in response to the delayed data signal and the timing signals, the delayed data signal and the timing signals having a phase relationship, each pair of delayed logic signals corresponding to one pair of logic signals;
• and
• a weighted current sum stage that generates the complementary output data signals as a first weighted data signal and a second weighted data signal, respectively, in response to both the plurality of pairs of logic signals and the plurality of pairs of delayed logic signals, each pair of logic signals controlling generation of both a first incremental portion of the first weighted data signal and a first incremental portion of the second weighted data signal, each pair of delayed logic signals controlling generation of both a second incremental portion of the first weighted data signal and a second incremental portion of the second weighted data signal,
• whereby an instantaneous value of the first weighted data signal is determined by summing together all of the incremental portions of the first weighted data signal while an instantaneous value of the second weighted data signal is determined by summing together all of the incremental portions of the second weighted data signal.

A waveshaping circuit for generating complementary output data signals, the waveshaping circuit comprising:

• an input stage that generates a plurality of pairs of logic signals within each period of a data signal in response to the data signal and a plurality of timing signal edges, the data signal and the plurality of timing signal edges having a phase relationship;
• a delayed input stage that generates a plurality of pairs of delayed logic signals within each period of a delayed data signal in response to the delayed data signal and the plurality of timing signal edges, the delayed data signal and the plurality of timing signal edges having a phase relationship, each pair of delayed logic signals corresponding to one pair of logic signals;
• and
• a weighted current sum stage that generates the complementary output data signals as a first weighted data signal and a second weighted data signal, respectively, in response to both the plurality of pairs of logic signals and the plurality of pairs of delayed logic signals, each pair of logic signals controlling generation of both a first incremental portion of the first weighted data signal and a first incremental portion of the second weighted data signal, each pair of delayed logic signals controlling generation of both a second incremental portion of the first weighted data signal and a second incremental portion of the second weighted data signal,
• whereby an instantaneous value of the first weighted data signal is determined by summing together all of the incremental portions of the first weighted data signal while an instantaneous value of the second weighted data signal is determined by summing together all of the incremental portions of the second weighted data signal.